Semiconductor device
    2.
    发明授权

    公开(公告)号:US10326626B2

    公开(公告)日:2019-06-18

    申请号:US16221667

    申请日:2018-12-17

    摘要: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

    Methods and systems for decoding data
    3.
    发明授权
    Methods and systems for decoding data 有权
    解码数据的方法和系统

    公开(公告)号:US08493247B2

    公开(公告)日:2013-07-23

    申请号:US13331708

    申请日:2011-12-20

    IPC分类号: H03M5/06

    摘要: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is generated by encoding source information using a Non Return to Zero Inverted (NRZI) code, selecting an NRZI decoding method based on one or more parameters associated with noise in the received coded bit stream, and generating a plurality of decisions by processing the received coded bit stream using the selected NRZI decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in the source information.

    摘要翻译: 提出了一种解码方法。 该方法包括以下步骤:接收通过使用非归零(NRZI)码对源信息进行编码而生成的编码比特流,基于与接收的编码比特流中的噪声相关的一个或多个参数选择NRZI解码方法 并且通过使用所选择的NRZI解码方法处理所接收的编码比特流来生成多个决定,其中所接收的编码比特流包括多个编码比特,并且所述多个决定是所述源中的多个源比特的估计 信息。

    Methods and systems for decoding data
    4.
    发明授权
    Methods and systems for decoding data 有权
    解码数据的方法和系统

    公开(公告)号:US08493246B2

    公开(公告)日:2013-07-23

    申请号:US13331625

    申请日:2011-12-20

    IPC分类号: H03M5/06

    摘要: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is encoded using a Non Return to Zero Inverted (NRZI) code and a 17 Parity Preserve/Prohibit (17PP) code, determining a 17PP modulated bit stream based upon the coded bit stream using a first selected decoding method, and generating a plurality of decisions by processing the 17PP modulated bit stream using a second selected decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in a source information.

    摘要翻译: 提出了一种解码方法。 该方法包括以下步骤:接收使用非归零(NRZI)码和17奇偶校验/禁止(17PP)码进行编码的编码比特流,基于编码比特流确定17PP调制比特流,使用 第一选择解码方法,并且通过使用第二选择的解码方法处理17PP调制比特流来生成多个决定,其中所接收的编码比特流包括多个编码比特,并且所述多个决定是多个 源信息中的源位。

    METHODS AND SYSTEMS FOR DECODING DATA
    5.
    发明申请
    METHODS AND SYSTEMS FOR DECODING DATA 有权
    解码数据的方法和系统

    公开(公告)号:US20130154858A1

    公开(公告)日:2013-06-20

    申请号:US13331708

    申请日:2011-12-20

    IPC分类号: H03M5/06 H03M7/00

    摘要: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is generated by encoding source information using a Non Return to Zero Inverted (NRZI) code, selecting an NRZI decoding method based on one or more parameters associated with noise in the received coded bit stream, and generating a plurality of decisions by processing the received coded bit stream using the selected NRZI decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in the source information.

    摘要翻译: 提出了一种解码方法。 该方法包括以下步骤:接收通过使用非归零(NRZI)码对源信息进行编码而生成的编码比特流,基于与接收的编码比特流中的噪声相关的一个或多个参数选择NRZI解码方法 并且通过使用所选择的NRZI解码方法处理所接收的编码比特流来生成多个决定,其中所接收的编码比特流包括多个编码比特,并且所述多个决定是所述源中的多个源比特的估计 信息。

    METHOD AND APPARATUS FOR LINE CODING
    6.
    发明申请
    METHOD AND APPARATUS FOR LINE CODING 有权
    线路编码的方法和装置

    公开(公告)号:US20110181450A1

    公开(公告)日:2011-07-28

    申请号:US12981739

    申请日:2010-12-30

    IPC分类号: H03M5/06

    CPC分类号: H03M5/145

    摘要: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n−1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n−1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n−1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n−1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

    摘要翻译: 本发明提供一种卷积行编码方法,包括:构建序列集中的每个序列的长度为n位的序列集; 选择序列集中的平衡序列,获得对应于平衡序列的n-1个比特的源数据; 对所述序列集中的不平衡序列进行汉明距离检测,以获得与所述不平衡序列相对应的n-1个比特的源数据; 根据操作差值对平衡序列和不平衡序列进行排序,并生成代码表,其中n-1位的源数据对应于n位的序列,并且代码表被设计用于线路编码; 并且在对n-1位的源数据进行编码时,根据代码表中的映射关系获得n位的编码结果。

    Method and apparatus of converting a series of data words into modulated signals

    公开(公告)号:US06995698B2

    公开(公告)日:2006-02-07

    申请号:US10748221

    申请日:2003-12-31

    IPC分类号: H03M5/06

    CPC分类号: H03M5/145 G11B20/1426

    摘要: The present invention relates to method and apparatus of modulating a series of data words into (d,k) constrained sequence in order to record onto a recording medium. The present method generates, for each data word, a number of alternative sequences by combining mutually different digital words with the data word, calculates for each alternative sequence a digital sum value (DSV) and a penalty based on respective consecutive-zeros sections within the sequence and a joining consecutive “zeros” to a previously-selected sequence, and selects one alternative sequence for recording onto a recordable medium based on the calculated DSV and penalties. Owing to the present invention, DC component of sequences to be recorded onto a recording medium is suppressed and stabilization of a reproduction clock is improved through writing more edge information (i.e., “1”s).

    Method for non-causal channel equalization
    8.
    发明申请
    Method for non-causal channel equalization 有权
    非因果信道均衡的方法

    公开(公告)号:US20050190607A1

    公开(公告)日:2005-09-01

    申请号:US11116612

    申请日:2005-04-29

    CPC分类号: H04L25/03012

    摘要: A system and method are provided for non-casual channel equalization in a communications system. The method comprises: establishing a first threshold (V1) to distinguish a high probability “1” first bit estimate; establishing a second threshold (V0) to distinguish a high probability “0” first bit estimate; establishing a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds; receiving a non-return to zero (NRZ) data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; in response to the comparisons, determining the value of the first bit. Establishing a third threshold (Vopt) includes: distinguishing NRZ data stream inputs below the first threshold and above the third threshold as a “0” if both the second and third bits are “1” values, and as a “1” if only one of the second and third values is a “1”, or if both the second and third bit values are a “0”; and, distinguishing NRZ data stream inputs above the second threshold and below the third threshold as a “1” if both the second and third bits are a “0” value, and as a “0” if only one of the second and third values is a “0”, or if both the second and third bit values are a “1”. The method further comprises: following the determination of the first bit values, FEC decoding the first bit values; and, using the FEC corrections of the first bit values to adjust the first, second, and third threshold values. Alternately, an averaging process is used to maintain the threshold values.

    摘要翻译: 在通信系统中提供用于非随意信道均衡的系统和方法。 该方法包括:建立第一阈值(V 1)以区分高概率“1”第一比特估计; 建立第二阈值(V 0)以区分高概率“0”第一比特估计; 建立第三阈值(Vopt)以区分第一和第二阈值之间的第一位估计; 接收不归零(NRZ)数据流; 将数据流中的第一比特估计与在第一比特之前接收的第二比特值进行比较; 将所述第一比特估计与所述第一比特之后接收的第三比特值进行比较; 响应于比较,确定第一位的值。 建立第三阈值(Vopt)包括:如果第二和第三位均为“1”,则将NRZ数据流输入区分为低于第一阈值且高于第三阈值为“0”,如果只有一个 第二和第三值的值为“1”,或者如果第二和第三比特值均为“0”; 以及如果第二和第三位均为“0”值,则将NRZ数据流输入区别为高于第二阈值且小于第三阈值的“1”,如果第二和第三值中只有一个值为“0” 是“0”,或者如果第二和第三位都是“1”。 该方法还包括:在确定第一比特值之后,FEC解码第一比特值; 并且使用第一位值的FEC校正来调整第一,第二和第三阈值。 或者,使用平均处理来维持阈值。

    Dual phase pulse modulation system
    9.
    发明申请
    Dual phase pulse modulation system 有权
    双相脉冲调制系统

    公开(公告)号:US20050078019A1

    公开(公告)日:2005-04-14

    申请号:US10961980

    申请日:2004-10-08

    IPC分类号: H03M5/08 H03M5/06 H03M9/00

    摘要: A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.

    摘要翻译: 描述了被配置为通过数据链路以串行方式使用双相位脉冲调制(DPPM)来发送和接收数据信号的系统。 数据链路可以是例如一根或两根非屏蔽双绞线(UTP)电缆。 示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口。 该界面可外部编程为特定的数据格式。 编码器耦合到可配置接口并将并行数据转换成串行输出数据,串行输出数据具有高和低数据脉冲,其中每个高和低数据脉冲被编码为具有2个不同数据脉冲宽度之一。 该系统还包括耦合到可配置接口的解码器,其能够将串行输入数据转换为并行数据。

    Precoder and optical duo-binary transmission apparatus using the same
    10.
    发明申请
    Precoder and optical duo-binary transmission apparatus using the same 失效
    预编码器和光二进制二进制传输装置使用

    公开(公告)号:US20050068209A1

    公开(公告)日:2005-03-31

    申请号:US10807048

    申请日:2004-03-23

    CPC分类号: H03M5/06 G11B20/10 H03M13/00

    摘要: A precoder for an optical duo-binary transmission apparatus disposing the precoder before a time division multiplexer includes a judgment unit for judging whether an odd number or even number of ‘1’s exist in data input signals of N channels inputted at an nth time of channel input. Further included in the precoder is a toggle unit for toggling an output signal of the judgment unit when the judgment is odd, and for determining an output value for one of the channels. The precoder also has an output unit for determining output values of other channels according to a respective data input signal and a predetermined channel from among the N channels.

    摘要翻译: 用于在时分多路复用器之前配置预编码器的光二元传输装置的预编码器包括判断单元,用于判断在第n时刻输入的N个信道的数据输入信号中是否存在“1”的奇数或偶数 的通道输入。 进一步包括在预编码器中的是用于当判断为奇数时用于切换判断单元的输出信号并且用于确定一个通道的输出值的切换单元。 预编码器还具有输出单元,用于根据相应的数据输入信号和N个信道中的预定信道来确定其它信道的输出值。