公开(公告)号：US11742031B2

公开(公告)日：2023-08-29

申请号：US17554710

申请日：2021-12-17

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa

IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C7/06 ,  G11C16/34 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  G11C7/10

CPC classification number: G11C16/26 ,  G11C7/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/3459 ,  H10B43/27 ,  H10B43/35 ,  G11C7/1039 ,  G11C16/0483 ,  G11C2211/562 ,  G11C2211/563 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

公开(公告)号：US20190130968A1

公开(公告)日：2019-05-02

申请号：US16219410

申请日：2018-12-13

Applicant: Toshiba Memory Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/26 ,  G06F11/10

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/563 ,  G11C2211/5642 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

公开(公告)号：US20190096491A1

公开(公告)日：2019-03-28

申请号：US15950757

申请日：2018-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G06F11/10

CPC classification number: G11C16/26 ,  G06F11/1008 ,  G06F11/1068 ,  G11C7/1006 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C2211/5642

Abstract: A nonvolatile memory device includes a plurality of memory cells and a page buffer including a plurality of page buffer units each connected to the plurality of memory cells through one bit line of a plurality of bit lines and configured to generate output data based on data states of the plurality of memory cells. A first page buffer unit of the plurality of page buffer units includes first to third latches which latch first to third read data at first to third time points, respectively by developing a voltage level of the sensing node, and a fourth latch which generates a fourth read data based on the second and third read data. The first page buffer unit is configured to selectively output the fourth read data as the output data, depending on whether an error correction of the first read data is possible.

公开(公告)号：US20180366178A1

公开(公告)日：2018-12-20

申请号：US15627947

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C11/24 ,  G11C11/4094 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C2211/5642

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.

公开(公告)号：US20180322929A1

公开(公告)日：2018-11-08

申请号：US15835586

申请日：2017-12-08

Applicant: SK hynix Inc.

Inventor： Hee Joung PARK ,  Kyeong Seung KANG ,  Won Chul SHIN ,  Dong Hyuk CHAE

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/32 ,  G11C2211/5642

Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.

公开(公告)号：US20180150400A1

公开(公告)日：2018-05-31

申请号：US15364831

申请日：2016-11-30

Applicant: SanDisk Technologies LLC

Inventor： Dinesh Agarwal

IPC: G06F12/0877 ,  G11C11/56 ,  G11C16/34 ,  G11C14/00 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G06F12/0215 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7203 ,  G11C2207/2245 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: Technology is described herein for caching residual data in latches during a write operation of non-volatile storage. When writing data at the request of a host, it is possible for there to be some residual data that cannot be programmed at two (or more) bits per memory cell into a page of memory cells, given the programming scheme being used. This residual data may be cached in latches. The residual data from the latches may be combined with other data from the host to increase programming speed when programming, for example, sequential data using a full sequence programming scheme. Also, caching the residual data in latches keeps write amplification low.

公开(公告)号：US09965388B2

公开(公告)日：2018-05-08

申请号：US15398181

申请日：2017-01-04

Applicant: SK hynix Inc.

Inventor： Ki Chang Chun ,  Hee Joung Park ,  Tae Seung Shin ,  Sung Lae Oh

IPC: G11C7/10 ,  G06F12/0802 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F2212/7203 ,  G11C7/1051 ,  G11C7/106 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.

公开(公告)号：US09947394B2

公开(公告)日：2018-04-17

申请号：US15361451

申请日：2016-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jun Yoon

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A nonvolatile memory device including a page buffer and a method of operating the nonvolatile memory device, the method including performing a first sensing operation using a first sensing voltage; precharging some bit lines from among a plurality of bit lines, according to first data stored in a first latch unit of a page buffer due to the first sensing operation; resetting the first latch unit; and performing a second sensing operation using a second sensing voltage.

公开(公告)号：US09941013B2

公开(公告)日：2018-04-10

申请号：US15280589

申请日：2016-09-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Maejima

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.

公开(公告)号：US20180096722A1

公开(公告)日：2018-04-05

申请号：US15831718

申请日：2017-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.