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公开(公告)号：US20170337130A1
公开(公告)日：2017-11-23
申请号：US15398181
申请日：2017-01-04
Applicant: SK hynix Inc.
Inventor： Ki Chang CHUN , Hee Joung PARK , Tae Seung SHIN , Sung Lae OH
IPC: G06F12/0802 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/16
CPC classification number: G06F12/0802 , G06F2212/60 , G06F2212/7203 , G11C7/1051 , G11C7/106 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C2211/5642 , G11C2211/5643
Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
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2.发明申请
公开(公告)号：US20210165603A1
公开(公告)日：2021-06-03
申请号：US17173794
申请日：2021-02-11
Applicant: SK hynix Inc.
Inventor： Byung In LEE , Hee Joung PARK , Keon Soo SHIM , Sang Heon LEE , Jae Il TAK
IPC: G06F3/06
Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
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公开(公告)号：US20200294597A1
公开(公告)日：2020-09-17
申请号：US16891561
申请日：2020-06-03
Applicant: SK hynix Inc.
Inventor： Hee Joung PARK , Kyeong Seung KANG , Won Chul SHIN
Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
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4.发明申请
公开(公告)号：US20200211650A1
公开(公告)日：2020-07-02
申请号：US16510071
申请日：2019-07-12
Applicant: SK hynix Inc.
Inventor： Byung In LEE , Hee Joung PARK , Keon Soo SHIM , Sang Heon LEE , Jae Il TAK
Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
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公开(公告)号：US20180322929A1
公开(公告)日：2018-11-08
申请号：US15835586
申请日：2017-12-08
Applicant: SK hynix Inc.
Inventor： Hee Joung PARK , Kyeong Seung KANG , Won Chul SHIN , Dong Hyuk CHAE
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/24 , G11C16/32 , G11C2211/5642
Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
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公开(公告)号：US20200294596A1
公开(公告)日：2020-09-17
申请号：US16891345
申请日：2020-06-03
Applicant: SK hynix Inc.
Inventor： Hee Joung PARK , Kyeong Seung KANG , Won Chul SHIN
Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
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公开(公告)号：US20190043584A1
公开(公告)日：2019-02-07
申请号：US15933979
申请日：2018-03-23
Applicant: SK hynix Inc.
Inventor： Hee Joung PARK , Kyeong Seung KANG , Won Chul SHIN
CPC classification number: G11C16/0483 , G11C11/5642 , G11C11/5671 , G11C16/08 , G11C16/24 , G11C16/26 , G11C2211/563 , G11C2211/5642 , G11C2211/5647
Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
