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公开(公告)号：US20240363169A1
公开(公告)日：2024-10-31
申请号：US18765164
申请日：2024-07-05
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
CPC分类号： G11C16/14 , G11C16/3445 , G11C16/0483
摘要： A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line. The control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage, apply an erasing voltage to the memory string in the erasing stage, apply a first voltage to the word line in a first stage of the verification stage, apply a second voltage lower than the first voltage to the word line in a second stage after the first stage, apply a first turn-on voltage to the second select line before applying the second voltage to the word line, and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.
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公开(公告)号：US12100456B2
公开(公告)日：2024-09-24
申请号：US18141207
申请日：2023-04-28
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
CPC分类号： G11C16/14 , G11C16/3445 , G11C16/0483
摘要： A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.
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3.发明公开公开(公告)号：US20230207027A1
公开(公告)日：2023-06-29
申请号：US18118565
申请日：2023-03-07
发明人： Yali Song , Jianquan Jia , Kaikai You , An Zhang , XiangNan Zhao , Ying Cui , Shan Li , Kaiwei Li , Lei Jin , Xueqing Huang , Meng Lou , Jinlong Zhang
CPC分类号： G11C16/3427 , G11C16/0483 , H10B41/27
摘要： A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.
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公开(公告)号：US20230162798A1
公开(公告)日：2023-05-25
申请号：US18090444
申请日：2022-12-28
发明人： Kaiwei Li , Jianquan Jia , Yuanyuan Min , Ying Cui , Yali Song , Hongtao Liu , Xinlei Jia , An Zhang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/28
摘要： A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.
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公开(公告)号：US20210249072A1
公开(公告)日：2021-08-12
申请号：US17241010
申请日：2021-04-26
发明人： Ying Cui , Jianquan Jia , Kaikai You
IPC分类号： G11C11/56 , G11C16/04 , G11C16/24 , H01L27/11556
摘要： A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.
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6.发明公开公开(公告)号：US20240321364A1
公开(公告)日：2024-09-26
申请号：US18223435
申请日：2023-07-18
发明人： Kaiwei Li , Jianquan Jia , Junbao Wang , An Zhang , Yali Song
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10
摘要： Implementations of the present disclosure disclose a memory operation method, a memory device, a memory system and an electronic apparatus. The memory device includes a memory stack structure, a select stack structure on the memory stack structure, a memory string including a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure, and including a first dummy memory cell adjacent to a plug, and a plurality of memory cells, a peripheral circuit connected with the memory string and configured to program the first dummy memory cell, and apply a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of one of the plurality of memory cells close to the plug.
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公开(公告)号：US20230268007A1
公开(公告)日：2023-08-24
申请号：US18141207
申请日：2023-04-28
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
CPC分类号： G11C16/14 , G11C16/3445 , G11C16/0483
摘要： A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.
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8.发明公开公开(公告)号：US20230260560A1
公开(公告)日：2023-08-17
申请号：US18139316
申请日：2023-04-25
发明人： Shan Li , Kaikai You , Ying Cui , Jianquan Jia , Kaiwei Li , An Zhang
IPC分类号： G11C8/08 , G11C7/14 , G11C8/14 , G11C11/4074 , G11C11/4094 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/30
CPC分类号： G11C8/08 , G11C7/14 , G11C8/14 , G11C11/4074 , G11C11/4094 , G11C16/0425 , G11C16/0466 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/30
摘要： In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.
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公开(公告)号：US20230030801A1
公开(公告)日：2023-02-02
申请号：US17965527
申请日：2022-10-13
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C11/408 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.
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10.发明申请公开(公告)号：US20220084573A1
公开(公告)日：2022-03-17
申请号：US17539133
申请日：2021-11-30
发明人： Shan Li , Kaikai You , Ying Cui , Jianquan Jia , Kaiwei Li , An Zhang
IPC分类号： G11C8/08 , G11C7/14 , G11C8/14 , G11C11/4074 , G11C11/4094 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/30
摘要： A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level. The controller is further configured to, after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line.
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