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公开(公告)号：US20190229113A1
公开(公告)日：2019-07-25
申请号：US15875568
申请日：2018-01-19
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Parag Upadhyaya , Kun-Yung Chang
IPC: H01L27/02 , H01L21/84 , H01L21/762 , H01L21/76 , H01L23/64 , H01L21/768 , H01L23/522
CPC classification number: H01L27/0288 , H01L21/7602 , H01L21/76297 , H01L21/76895 , H01L21/84 , H01L23/5222 , H01L23/5226 , H01L23/645
Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.
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公开(公告)号：US09960902B1
公开(公告)日：2018-05-01
申请号：US15380653
申请日：2016-12-15
Applicant: Xilinx, Inc.
Inventor： Winson Lin , Yu Xu , Caleb S. Leung , Alan C. Wong , Christopher J. Borrelli , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L1/205 , H03L7/0814 , H04L7/0037 , H04L7/033 , H04L7/0337
Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.
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公开(公告)号：US20180102797A1
公开(公告)日：2018-04-12
申请号：US15837791
申请日：2017-12-11
Applicant: Xilinx, Inc.
Inventor： Siok Wei Lim , Kok Lim Chan , Kee Hian Tan , Hongyuan Zhao , Chin Yang Koay , Yohan Frans , Kun-Yung Chang
IPC: H04B1/04 , H03M9/00 , H02M3/158 , H03K17/687
CPC classification number: H04B1/04 , H02M3/158 , H03K17/163 , H03K17/6872 , H03K19/0175 , H03M9/00
Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
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公开(公告)号：US09887710B1
公开(公告)日：2018-02-06
申请号：US15227853
申请日：2016-08-03
Applicant: Xilinx, Inc.
Inventor： Siok Wei Lim , Kok Lim Chan , Kee Hian Tan , Hongyuan Zhao , Chin Yang Koay , Yohan Frans , Kun-Yung Chang
IPC: H04B1/04 , H03K17/687 , H03M9/00 , H02M3/158
CPC classification number: H04B1/04 , H02M3/158 , H03K17/163 , H03K17/6872 , H03K19/0175 , H03M9/00
Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
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公开(公告)号：US09882703B1
公开(公告)日：2018-01-30
申请号：US15346434
申请日：2016-11-08
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Winson Lin , Caleb S. Leung , Alan C. Wong , Christopher J. Borrelli , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L43/16 , H04L7/0025 , H04L7/0083 , H04L7/033 , H04L25/03 , H04L43/028
Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.
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Patent Agency Ranking
公开(公告)号：US20160352557A1
公开(公告)日：2016-12-01
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
Abstract translation: 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。
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公开(公告)号：US09413524B1
公开(公告)日：2016-08-09
申请号：US14887744
申请日：2015-10-20
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L7/0087 , H04L7/0025 , H04L7/0337
Abstract: In an example, an apparatus for CDR includes at least one data register, at least one edge register having an input coupled to an output of the at least one data register, and a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge register. The apparatus further includes a frequency accumulator coupled to an output of the phase detector, a dynamic gain circuit coupled to the output of the phase detector, and a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output of the dynamic gain circuit and an output of the frequency accumulator.
Abstract translation: 在一个示例中，用于CDR的装置包括至少一个数据寄存器，至少一个边缘寄存器，其具有耦合到所述至少一个数据寄存器的输出的输入，以及相位检测器，其具有耦合到所述至少一个 数据寄存器和至少一个边沿寄存器的输出。 该装置还包括耦合到相位检测器的输出的频率累加器，耦合到相位检测器的输出的动态增益电路，以及相位累加器和代码发生器电路，被配置为基于输出来产生用于控制相位内插器的代码 的动态增益电路和频率累加器的输出。
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公开(公告)号：US09379880B1
公开(公告)日：2016-06-28
申请号：US14795150
申请日：2015-07-09
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L7/0337
Abstract: Clock data recovery can be accomplished using a phase change determination circuit that generates, based upon detected phase differences between a capture clock signal and data signal, a delta signal and a delta selection signal. A calculation circuit generates a set of phase interpolation (PI) codes from prior and speculative values of the delta signal. A selection circuit selects, in response to the delta selection signal, between the sets of PI codes, which are provided as an output of the clock data recovery device.
Abstract translation: 时钟数据恢复可以使用相位变化确定电路来实现，相位变化确定电路基于检测到的捕获时钟信号和数据信号之间的相位差产生增量信号和增量选择信号。 计算电路从增量信号的先验值和推测值生成一组相位插值（PI）码。 选择电路响应于增量选择信号选择作为时钟数据恢复装置的输出提供的PI代码组。
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公开(公告)号：US11107770B1
公开(公告)日：2021-08-31
申请号：US16454629
申请日：2019-06-27
Applicant: XILINX, INC.
Inventor： Suresh Ramalingam , Kun-Yung Chang , Yohan Frans , Chuan Xie , Mayank Raj
IPC: H01L23/538 , H01L23/13 , H01L23/49 , H01L25/18 , G02B6/42 , H01L25/00 , H01L23/00 , H01L21/48 , H01L23/498
Abstract: An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.
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公开(公告)号：US10054806B2
公开(公告)日：2018-08-21
申请号：US15346474
申请日：2016-11-08
Applicant: Xilinx, Inc.
Inventor： Sen Lin , Kun-Yung Chang , Austin H. Lesea
IPC: H04B10/04 , G02F1/025 , H04B10/516 , G02F1/015
CPC classification number: G02F1/025 , G02F2001/0157 , G02F2201/122 , G02F2201/16 , G02F2201/58 , H04B10/516
Abstract: Systems and methods therefor relating generally to electro-absorption modulation are disclosed. In a system thereof, a waveguide is for propagating an optical signal. A segmented electro-absorption modulator (“SEAM”) includes: a segmented anode having at least two anode segments spaced apart from one another alongside a first side of the waveguide; and a segmented cathode having at least two cathode segments spaced apart from one another alongside a second side of the waveguide corresponding to the at least two anode segments.
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