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1.发明申请公开(公告)号：US20170019278A1
公开(公告)日：2017-01-19
申请号：US14798364
申请日：2015-07-13
Applicant: Xilinx, Inc.
Inventor： Vassili Kireev , Yu Liao
IPC: H04L25/49
CPC classification number: H04L25/4919 , H03K5/2481 , H03K19/09425 , H03K19/17788 , H04L25/0272 , H04L25/028 , H04L25/4917
Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.
Abstract translation: 公开了一种用于在集成电路的发射机中产生调制信号的电路。 该电路包括具有用于接收一对差分输入信号的第一输入信号的第一电流路径和用于接收该对差分输入信号的第二输入信号的第二电流路径的发射器驱动器电路，该发射器驱动电路包括： 耦合到第一电流路径和第二电流路径中的每一个的尾部电流路径; 耦合在第一参考电压和地之间的第一电流源，其中所述第一电流源的第一电流与所述尾电流路径的尾电流成比例; 耦合在所述第一参考电压和所述发射器驱动器电路的第一输出节点之间的第一上拉电流源; 以及耦合在所述发射器驱动器电路的所述第一参考电压和第二输出节点之间的第二上拉电流源。 还公开了一种在集成电路的发射机中产生调制信号的方法。
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公开(公告)号：US09438409B1
公开(公告)日：2016-09-06
申请号：US14789738
申请日：2015-07-01
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang
CPC classification number: H04L25/03057 , H04L7/0062 , H04L7/0087
Abstract: In an example, an apparatus for clock data recovery (CDR) includes a data slicer operable to generate data samples derived from a transmitted signal, and an error slicer operable to generate error samples derived from a transmitted signal. The apparatus further includes a CDR circuit operable to generate sampling clock phase for the data slicer and the error slicer from output of the data samples and the error samples. The apparatus further includes a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a function of at least one pre-cursor data sample, at least one post-cursor data sample, or a combination of at least one pre-cursor data sample and at least one post-cursor data sample.
Abstract translation: 在一个示例中，用于时钟数据恢复（CDR）的装置包括可操作以产生从发送信号导出的数据样本的数据限幅器，以及用于产生从发送信号导出的误差样本的差错限幅器。 该装置还包括CDR电路，可操作以从数据样本和误差样本的输出产生数据限幅器和误差限幅器的采样时钟相位。 所述装置还包括判定适配电路，其可操作以设置所述误差限幅器的判定阈值，其中，对于所述数据样本的每个主光标数据采样，所述判定适配电路可操作以基于至少一个 前标数据样本，至少一个后标记数据样本或至少一个前置标准数据样本和至少一个后视标数据样本的组合。
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公开(公告)号：US20160352557A1
公开(公告)日：2016-12-01
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
Abstract translation: 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。
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公开(公告)号：US09674015B2
公开(公告)日：2017-06-06
申请号：US14798364
申请日：2015-07-13
Applicant: Xilinx, Inc.
Inventor： Vassili Kireev , Yu Liao
IPC: H04L25/49 , H03K5/24 , H03K19/094 , H03K19/177
CPC classification number: H04L25/4919 , H03K5/2481 , H03K19/09425 , H03K19/17788 , H04L25/0272 , H04L25/028 , H04L25/4917
Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.
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公开(公告)号：US09276782B1
公开(公告)日：2016-03-01
申请号：US14698588
申请日：2015-04-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Liao
IPC: H04L25/03
CPC classification number: H04L25/03146 , H04L25/03057
Abstract: In a receiver, there is a precursor iterative canceller (“PIC”) having first and second paths. A postcursor decision block is coupled to the PIC to provide a decision signal thereto. The PIC includes: comparators for receiving an input signal and corresponding threshold inputs for precursor ISI speculation; and select circuits for selecting a first speculative input for the first path and a second speculative input for the second path, respectively associated with a negative precursor contribution and a positive precursor contribution. The first path and the second path in combination include at least a first stage and a second stage for processing the first speculative input and the second speculative input. The decision signal is provided to the first stage and to the select circuits. The select circuits are coupled to receive the decision signal for selection of the first speculative input and the second speculative input.
Abstract translation: 在接收机中，存在具有第一和第二路径的前体迭代消除器（“PIC”）。 后端决策块被耦合到PIC以向其提供判决信号。 PIC包括：用于接收输入信号的比较器和用于前体ISI投机的相应阈值输入; 以及选择用于选择第一路径的第一推测输入和用于第二路径的第二推测输入，分别与负前驱贡献和正前驱贡献相关联。 组合的第一路径和第二路径包括用于处理第一推测输入和第二推测输入的至少第一级和第二级。 决定信号被提供给第一级和选择电路。 选择电路被耦合以接收用于选择第一推测输入和第二推测输入的判定信号。
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Patent Agency Ranking
6.发明授权Circuits for and methods of robust adaptation of a continuous time linear equalizer circuit 有权电路和连续时间线性均衡电路的鲁棒适应方法公开(公告)号：US09461851B1
公开(公告)日：2016-10-04
申请号：US14885666
申请日：2015-10-16
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang
CPC classification number: H04L27/01 , H04L25/0212 , H04L25/03019 , H04L25/03057 , H04L25/03885
Abstract: A circuit for enabling an adaptation of an equalization circuit is described. The circuit comprises a continuous time linear equalizer configured to receive an input data signal and generate an equalized input data signal; a decision circuit configured to receive the equalized input data signal, wherein the decision circuit generates an estimate of the input data signal; channel estimation circuit configured to receive the estimate of the input data signal and an error signal to generate an impulse response estimate of an equivalent channel; a frequency response computation circuit configured to receive the impulse response estimate of the equivalent channel and generate a channel frequency response; and a continuous time linear equalizer control circuit configured to receive the channel frequency response and to generate a CTLE adaptation signal for controlling the continuous time linear equalizer.
Abstract translation: 描述了一种用于实现均衡电路的适配的电路。 电路包括连续时间线性均衡器，被配置为接收输入数据信号并产生均衡的输入数据信号; 判定电路，被配置为接收所述均衡输入数据信号，其中所述判定电路生成所述输入数据信号的估计; 信道估计电路，被配置为接收输入数据信号的估计和误差信号，以产生等效信道的脉冲响应估计; 频率响应计算电路，被配置为接收等效信道的脉冲响应估计并产生信道频率响应; 以及连续时间线性均衡器控制电路，被配置为接收信道频率响应并产生用于控制连续时间线性均衡器的CTLE自适应信号。
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7.发明授权Circuits for and methods of filtering inter-symbol interference for SerDes applications 有权用于SerDes应用的滤波符号间干扰的电路和方法公开(公告)号：US09313054B1
公开(公告)日：2016-04-12
申请号：US14617015
申请日：2015-02-09
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Hongtao Zhang , Geoffrey Zhang , Kun-Yung Chang
CPC classification number: H04L25/03019 , H04L2025/03484
Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.
Abstract translation: 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字样本的第一级。 第一阶段基于数字样本产生第一决策输出。 第二级被耦合以接收输入信号的数字样本。 第二级包括接收第一判定输出并基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰的第二判定输出的滤波器。 还描述了一种对集成电路中符号间干扰进行滤波的方法。
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公开(公告)号：US09654327B2
公开(公告)日：2017-05-16
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
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9.发明授权公开(公告)号：US09379920B1
公开(公告)日：2016-06-28
申请号：US14707919
申请日：2015-05-08
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Hongtao Zhang , Kun-Yung Chang , Geoffrey Zhang
CPC classification number: H04L25/03057 , H04L25/03 , H04L25/03146 , H04L25/03878 , H04L25/03885 , H04L27/01 , H04L2025/0349 , H04L2025/03503
Abstract: In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.
Abstract translation: 在接收机中，判决反馈均衡器（“DFE”）接收模拟输入信号。 DFE包括用于从模拟输入信号减去加权后移判定的减法模块以提供模拟输出信号。 耦合到DFE的后端判定块将模拟输出信号与后移系数的正值和负值进行比较，以响应于先前的基于后期的判定来提供用于选择当前基于后台的判定的第一和第二可能决定。 前体消除块接收模拟输出信号，先前的基于后期的判定和当前的基于前后的判定，用于为模拟输入信号的先前样本提供数字输出信号。
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公开(公告)号：US09313017B1
公开(公告)日：2016-04-12
申请号：US14737330
申请日：2015-06-11
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Zhaoyin D. Wu , Kun-Yung Chang
CPC classification number: H04L7/0087 , H04L7/0025 , H04L7/0062 , H04L25/03
Abstract: In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.
Abstract translation: 在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。 定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。 定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。 环路滤波器耦合到定时误差检测器以接收定时误差值。 相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。
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