公开(公告)号：US10199341B2

公开(公告)日：2019-02-05

申请号：US15224767

申请日：2016-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/00

Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

公开(公告)号：US20170317040A1

公开(公告)日：2017-11-02

申请号：US15224767

申请日：2016-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02205 ,  H01L2224/0221 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/81192 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/014

Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

公开(公告)号：US20170148761A1

公开(公告)日：2017-05-25

申请号：US15400608

申请日：2017-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

公开(公告)号：US20170053859A1

公开(公告)日：2017-02-23

申请号：US14982099

申请日：2015-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai

IPC: H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/053

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2221/68331 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing an interposer having a plurality of conductive vias and at least an opening formed at a periphery of the conductive vias; disposing at least an electronic element on the interposer; and bonding a cover plate to the electronic element and forming an encapsulant between the cover plate and the interposer so as to encapsulate the electronic element and fill the opening, thus allowing the encapsulant in the opening to come into contact with air. As such, during a subsequent high temperature process, evaporated solvents can flow out of the encapsulant through the opening without forming bubbles in the encapsulant, thereby preventing a bubble explosion from occurring. The invention further provides an electronic package.

Abstract translation: 提供一种制造电子封装的方法，包括以下步骤：提供具有多个导电通孔和形成在导电通孔周边的至少一个开口的插入件; 将至少一个电子元件设置在所述插入器上; 并将盖板接合到电子元件上，并在盖板和插入件之间形成密封剂，以封装电子元件并填充开口，从而允许开口中的密封剂与空气接触。 因此，在随后的高温过程中，蒸发的溶剂可以通过开口流出密封剂，而不会在密封剂中形成气泡，从而防止发生气泡爆炸。 本发明还提供一种电子封装。

公开(公告)号：US20150132893A1

公开(公告)日：2015-05-14

申请号：US14604128

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US20150035163A1

公开(公告)日：2015-02-05

申请号：US14012402

申请日：2013-08-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将半导体元件放置在载体的凹槽中; 在所述半导体元件上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分以将所述载体的第二载体保持在所述凹槽的侧壁上，以使所述第二部分用作支撑部分。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。

公开(公告)号：US20140264928A1

公开(公告)日：2014-09-18

申请号：US13922798

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/52 ,  H01L21/56 ,  H01L23/28

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：在插入件上设置多个第一半导体元件; 在所述插入件上形成用于封装所述第一半导体元件的第一密封剂; 在所述第一半导体元件上设置多个第二半导体元件; 在所述第一半导体元件和所述第一密封剂上形成用于封装所述第二半导体元件的第二密封剂; 并使插入件变薄，从而减小整体堆叠厚度并防止插入件的翘曲。

公开(公告)号：US20140191386A1

公开(公告)日：2014-07-10

申请号：US13894716

申请日：2013-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Mei-Chin Lee ,  Wang-Ting Chen ,  Chi-Tung Yeh ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/48 ,  H01L23/373

CPC classification number: H01L23/3738 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer.

Abstract translation: 提供半导体封装。 半导体封装包括衬底; 半导体元件具有相反的有源和非活性表面，并经由其活性表面设置在衬底上，其中半导体元件的非活性表面被粗糙化; 接合到半导体元件的非活性表面的导热层; 以及布置在导热层上的散热器。 粗糙化的非活性表面促进了半导体元件和导热层之间的结合，从而消除了执行镀金工艺和使用焊剂的需要，从而减少导热层中空隙的形成。

公开(公告)号：US20140008819A1

公开(公告)日：2014-01-09

申请号：US13660249

申请日：2012-10-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/488 ,  H01L21/50 ,  B32B37/12 ,  H01L23/12

CPC classification number: H01L23/12 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.

Abstract translation: 提供了一种基板结构，包括基板和结合到基板的表面的加强件。 加强构件具有小于衬底的CTE（热膨胀系数），以便有效地防止对衬底结构发生翘曲。

公开(公告)号：US10049975B2

公开(公告)日：2018-08-14

申请号：US15258303

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/498 ,  H01L23/00

Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.