公开(公告)号：US11804483B2

公开(公告)日：2023-10-31

申请号：US17177824

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823481

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US11784260B2

公开(公告)日：2023-10-10

申请号：US17863127

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Dong-Soo Lee ,  Sang-Yong Kim ,  Jin-Kyu Jang ,  Won-Keun Chung ,  Sang-Jin Hyun

IPC: H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/7926 ,  B82Y10/00 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L21/823462 ,  H01L21/823857

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US11127739B2

公开(公告)日：2021-09-21

申请号：US16028272

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/51

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

公开(公告)号：US20200098751A1

公开(公告)日：2020-03-26

申请号：US16401362

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US20190312030A1

公开(公告)日：2019-10-10

申请号：US16432233

申请日：2019-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Kyu Park ,  Jae-Yeol Song ,  Hoon-Joo Na ,  Yoon-Tae Hwang ,  Ki-Joong Yoon ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L29/43

Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

公开(公告)号：US10177042B2

公开(公告)日：2019-01-08

申请号：US15193805

申请日：2016-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Keun Chung ,  Hu-Yong Lee ,  Taek-Soo Jeon ,  Sang-Jin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

公开(公告)号：US11495597B2

公开(公告)日：2022-11-08

申请号：US17030556

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Kyu Park ,  Jae-Yeol Song ,  Hoon-Joo Na ,  Yoon-Tae Hwang ,  Ki-Joong Yoon ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

公开(公告)号：US10950602B2

公开(公告)日：2021-03-16

申请号：US16401362

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US10312340B2

公开(公告)日：2019-06-04

申请号：US15717324

申请日：2017-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Don Kim ,  Oh-Seong Kwon ,  Hoon-Joo Na ,  Hyeok-Jun Son ,  Jae-Yeol Song ,  Sung-Kee Han ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

公开(公告)号：US10134856B2

公开(公告)日：2018-11-20

申请号：US15254297

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da-Il Eom ,  Jeong-Ik Kim ,  Ja-Hum Ku ,  Chul-Sung Kim ,  Jun-Ki Park ,  Sang-Jin Hyun

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.