公开(公告)号：US09195579B2

公开(公告)日：2015-11-24

申请号：US13754161

申请日：2013-01-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation, Sungkyunkwan University

Inventor： Oh-Seong Kwon ,  Hwansoo Han ,  Sun-Young Lim ,  Seonggun Kim

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/121 ,  G06F2212/205 ,  G06F2212/222

Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

Abstract translation: 存储器系统包括中央处理单元（CPU），电耦合到CPU的非易失性存储器和主存储器，其被配置为响应于由所述主存储器发出的第一命令来交换其中的目标代码页的输入代码页 中央处理器。 主存储器可被配置为在主存储器的页面容量处于阈值容量的情况下将主存储器中的目标代码页交换到非易失性存储器。 CPU还可以被配置为在目标代码页上执行使用分析频率，以确定目标代码页是否被交换到非易失性存储器或被丢弃。 输入代码页可以由磁盘驱动器存储设备提供，并且主存储器可以是易失性存储器。

公开(公告)号：US10312340B2

公开(公告)日：2019-06-04

申请号：US15717324

申请日：2017-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Don Kim ,  Oh-Seong Kwon ,  Hoon-Joo Na ,  Hyeok-Jun Son ,  Jae-Yeol Song ,  Sung-Kee Han ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

公开(公告)号：US10013341B2

公开(公告)日：2018-07-03

申请号：US15371825

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Oh-Seong Kwon ,  Jinhyun Kim ,  Won-Hyung Song ,  Jihyun Choi

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G11C8/18 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G06F12/00 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/02 ,  G11C5/04 ,  G11C7/1042 ,  G11C7/1057 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2209

Abstract: A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.

公开(公告)号：US09620180B2

公开(公告)日：2017-04-11

申请号：US14722158

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young Lim ,  Dong-Yang Lee ,  Young-Jin Cho ,  Oh-Seong Kwon

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

公开(公告)号：US08873328B2

公开(公告)日：2014-10-28

申请号：US14037544

申请日：2013-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Shik Shin ,  Yunseok Yang ,  Oh-Seong Kwon

IPC: G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  G11C11/16

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C11/1675

Abstract: A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括连接到位线和字线的存储单元; 字线解码器，被配置为将字线电压施加到所述字线; 配置为选择位线的至少一个位线的位线选择器; 控制逻辑，被配置为控制字线解码器和位线选择器，使得写入数据被编程在存储单元阵列中; 和突发断电（SPO）检测电路，其中SPO检测电路包括：感测单元; 第一驱动器，被配置为向所述感测单元提供第一电压; 以及第二驱动器，被配置为向所述感测单元提供第二电压，其中所述感测单元的编程状态根据所述第一驱动器和所述第二驱动器被断电的顺序或时间差而变得不同。

公开(公告)号：US20130262738A1

公开(公告)日：2013-10-03

申请号：US13754161

申请日：2013-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  RESEARCH & BUSINESS FOUNDATION, SUNGKYUNKWAN UNIVERSITY

Inventor： Oh-Seong Kwon ,  Hwansoo Han ,  Sun-Young Lim ,  Seonggun Kim

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/121 ,  G06F2212/205 ,  G06F2212/222

Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

Abstract translation: 存储器系统包括中央处理单元（CPU），电耦合到CPU的非易失性存储器和主存储器，其被配置为响应于由所述主存储器发出的第一命令来交换其中的目标代码页的输入代码页 中央处理器。 主存储器可被配置为在主存储器的页面容量处于阈值容量的情况下将主存储器中的目标代码页交换到非易失性存储器。 CPU还可以被配置为在目标代码页上执行使用分析频率，以确定目标代码页是否被交换到非易失性存储器或被丢弃。 输入代码页可以由磁盘驱动器存储设备提供，并且主存储器可以是易失性存储器。

公开(公告)号：USRE49151E1

公开(公告)日：2022-07-26

申请号：US16381104

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young Lim ,  Dong-Yang Lee ,  Young-Jin Cho ,  Oh-Seong Kwon

IPC: G11C7/10 ,  G06F13/16

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.