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    Memory system and electronic device
    3.
    发明授权
    Memory system and electronic device 有权

    公开(公告)号：US09620180B2

    公开(公告)日：2017-04-11

    申请号：US14722158

    申请日：2015-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young Lim ,  Dong-Yang Lee ,  Young-Jin Cho ,  Oh-Seong Kwon

    IPC: G11C7/10

    CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

    Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

    PAGE REPLACEMENT METHOD AND MEMORY SYSTEM USING THE SAME
    4.
    发明申请
    PAGE REPLACEMENT METHOD AND MEMORY SYSTEM USING THE SAME 有权
    使用相同的页替换方法和存储器系统

    公开(公告)号：US20130262738A1

    公开(公告)日：2013-10-03

    申请号：US13754161

    申请日：2013-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  RESEARCH & BUSINESS FOUNDATION, SUNGKYUNKWAN UNIVERSITY

    Inventor： Oh-Seong Kwon ,  Hwansoo Han ,  Sun-Young Lim ,  Seonggun Kim

    IPC: G06F12/02

    CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/121 ,  G06F2212/205 ,  G06F2212/222

    Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

    Abstract translation: 存储器系统包括中央处理单元（CPU），电耦合到CPU的非易失性存储器和主存储器，其被配置为响应于由所述主存储器发出的第一命令来交换其中的目标代码页的输入代码页 中央处理器。 主存储器可被配置为在主存储器的页面容量处于阈值容量的情况下将主存储器中的目标代码页交换到非易失性存储器。 CPU还可以被配置为在目标代码页上执行使用分析频率，以确定目标代码页是否被交换到非易失性存储器或被丢弃。 输入代码页可以由磁盘驱动器存储设备提供，并且主存储器可以是易失性存储器。

    Memory system and electronic device
    5.
    再颁专利
    Memory system and electronic device 有权

    公开(公告)号：USRE49151E1

    公开(公告)日：2022-07-26

    申请号：US16381104

    申请日：2019-04-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young Lim ,  Dong-Yang Lee ,  Young-Jin Cho ,  Oh-Seong Kwon

    IPC: G11C7/10 ,  G06F13/16

    Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

    Memory system capable of re-mapping address
    6.
    发明授权
    Memory system capable of re-mapping address 有权

    公开(公告)号：US10083764B2

    公开(公告)日：2018-09-25

    申请号：US14524476

    申请日：2014-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mi-Kyoung Park ,  Dong-Yang Lee ,  Sun-Young Lim ,  Bu-Il Jung ,  Ju-Yun Jung ,  Sung-Ho Cho ,  Hee-Joo Choi ,  Min-Yeab Choo ,  Hyuk Han

    IPC: G11C29/00 ,  G11C8/06 ,  G11C29/44

    CPC classification number: G11C29/76 ,  G11C8/06 ,  G11C2029/4402

    Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

    Memory system having first and second memory devices and driving method thereof
    7.
    发明授权
    Memory system having first and second memory devices and driving method thereof 有权
    具有第一和第二存储器件的存储器系统及其驱动方法

    公开(公告)号：US09552314B2

    公开(公告)日：2017-01-24

    申请号：US14090521

    申请日：2013-11-26

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Sun-Young Lim ,  Dong-Hwi Kim

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F13/1694

    Abstract: A memory system includes first and second memory devices, a memory controller configured to control the second memory device, to store a request signal to access the first memory device, and to generate an interrupt signal, and a host configured to receive the request signal in response to the interrupt signal.

    Abstract translation: 存储器系统包括第一和第二存储器设备，配置成控制第二存储器件的存储器控​​制器，存储访问第一存储器件的请求信号，并产生中断信号，以及被配置为接收请求信号的主机 响应中断信号。

    Systems and methods for write and flush support in hybrid memory
    9.
    发明授权
    Systems and methods for write and flush support in hybrid memory 有权

    公开(公告)号：US11175853B2

    公开(公告)日：2021-11-16

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/00 ,  G06F12/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/02

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

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