公开(公告)号：US12086011B2

公开(公告)日：2024-09-10

申请号：US18144956

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok Oh

IPC: G06F1/32 ,  G06F1/3234 ,  G11C11/40 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F1/3275 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

公开(公告)号：US11790963B2

公开(公告)日：2023-10-17

申请号：US17708414

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok Oh

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G11C5/14 ,  G06F12/0811

CPC classification number: G11C7/222 ,  G06F12/0811 ,  G06F13/1668 ,  G11C5/14 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

Abstract: An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.

公开(公告)号：US11749337B2

公开(公告)日：2023-09-05

申请号：US17807163

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20230066632A1

公开(公告)日：2023-03-02

申请号：US18047614

申请日：2022-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US11062744B2

公开(公告)日：2021-07-13

申请号：US16262250

申请日：2019-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US10521153B2

公开(公告)日：2019-12-31

申请号：US15492436

申请日：2017-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young Lim ,  Ki-Seok Oh ,  Sungyong Seo ,  Youngjin Cho ,  Insu Choi

IPC: G06F3/06 ,  G11C11/406 ,  G11C14/00

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

公开(公告)号：US20190304517A1

公开(公告)日：2019-10-03

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20190237127A1

公开(公告)日：2019-08-01

申请号：US16230185

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US12020767B2

公开(公告)日：2024-06-25

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/222

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US11749338B2

公开(公告)日：2023-09-05

申请号：US17816138

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.