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1.发明申请公开(公告)号：US20190304517A1
公开(公告)日：2019-10-03
申请号：US16363077
申请日：2019-03-25
发明人： Dae-Sik Moon , Kyung-soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US12106794B2
公开(公告)日：2024-10-01
申请号：US18330527
申请日：2023-06-07
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G06F3/06 , G11C7/22 , G11C11/4076 , G11C11/409
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
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公开(公告)号：US10885950B2
公开(公告)日：2021-01-05
申请号：US16363077
申请日：2019-03-25
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US12020767B2
公开(公告)日：2024-06-25
申请号：US17539761
申请日：2021-12-01
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
CPC分类号： G11C7/1048 , G11C7/1084 , G11C7/222
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US11749338B2
公开(公告)日：2023-09-05
申请号：US17816138
申请日：2022-07-29
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
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公开(公告)号：US11749337B2
公开(公告)日：2023-09-05
申请号：US17807163
申请日：2022-06-16
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
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公开(公告)号：US09742355B2
公开(公告)日：2017-08-22
申请号：US14959195
申请日：2015-12-04
发明人： Yoon-Joo Eom , Seung-Jun Bae , Dae-Sik Moon , Joon-Young Park , Min-Su Ahn
IPC分类号： H03F3/45 , H03D7/14 , H03K19/003
CPC分类号： H03D7/1441 , H03F3/45183 , H03F2203/45051 , H03F2203/45466 , H03F2203/45674 , H03F2203/45702 , H03K19/00361
摘要： A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.
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公开(公告)号：US12033686B2
公开(公告)日：2024-07-09
申请号：US18314243
申请日：2023-05-09
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/4076 , G06F3/06 , G11C7/22 , G11C11/409
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
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公开(公告)号：US11423971B2
公开(公告)日：2022-08-23
申请号：US17564564
申请日：2021-12-29
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
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公开(公告)号：US11211102B2
公开(公告)日：2021-12-28
申请号：US17104114
申请日：2020-11-25
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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