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公开(公告)号：US10649894B2
公开(公告)日：2020-05-12
申请号：US16195533
申请日：2018-11-19
发明人： Han-Ju Lee , Youngjin Cho , Sungyong Seo , Youngkwang Yoo
摘要： The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.
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公开(公告)号：US20190278487A1
公开(公告)日：2019-09-12
申请号：US16414893
申请日：2019-05-17
发明人： Youngjin CHO , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F3/06 , G06F12/0893 , G11C11/00 , G06F13/16 , G06F12/0868 , G11C16/26 , G11C16/10
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
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公开(公告)号：US10089031B2
公开(公告)日：2018-10-02
申请号：US15019419
申请日：2016-02-09
发明人： Sungyong Seo , Yeong-Jae Woo , MoonSang Kwon , Sunmi Lee
摘要： Data storage is provided which includes a nonvolatile memory device including a plurality of memory blocks divided into a first region being an over provisioning region and a second region, and a storage controller allocating at least one memory block, corresponding to an unconcerned sector, from among memory blocks of the second region to the first region. It may be possible to adjust the number of reserved memory blocks in the over provisioning region.
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公开(公告)号：US10152413B2
公开(公告)日：2018-12-11
申请号：US15083425
申请日：2016-03-29
发明人： Han-Ju Lee , Youngjin Cho , Sungyong Seo , Youngkwang Yoo
摘要： The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.
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公开(公告)号：US10521153B2
公开(公告)日：2019-12-31
申请号：US15492436
申请日：2017-04-20
发明人： Sun-Young Lim , Ki-Seok Oh , Sungyong Seo , Youngjin Cho , Insu Choi
IPC分类号： G06F3/06 , G11C11/406 , G11C14/00
摘要： A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.
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公开(公告)号：US10303372B2
公开(公告)日：2019-05-28
申请号：US15366137
申请日：2016-12-01
发明人： Youngjin Cho , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F13/16 , G06F3/06 , G11C16/26 , G11C16/10 , G06F12/0868 , G06F12/0893 , G11C11/00
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
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公开(公告)号：US20170168931A1
公开(公告)日：2017-06-15
申请号：US15354354
申请日：2016-11-17
发明人： Chankyung Kim , Uksong Kang , Sanguhn Cha , Sungyong Seo , Youngjin Cho , Seongil O
IPC分类号： G06F12/02 , G11C14/00 , G11C7/10 , G11C11/406 , G11C11/4093 , G11C11/4096
CPC分类号： G06F12/0871 , G06F11/1064 , G06F12/0802 , G06F12/0804 , G06F12/0853 , G06F12/0868 , G06F12/0895 , G06F2212/1004 , G06F2212/1028 , G06F2212/205 , G06F2212/214 , G06F2212/22 , G06F2212/313 , G06F2212/60 , G06F2212/601 , G06F2212/7203 , G11C5/04 , G11C7/1072 , G11C11/005 , G11C11/4093 , G11C16/0483
摘要： A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.
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公开(公告)号：US11614866B2
公开(公告)日：2023-03-28
申请号：US17389834
申请日：2021-07-30
发明人： Youngjin Cho , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F3/06 , G11C16/26 , G11C16/10 , G06F12/0868 , G06F12/0893 , G11C11/00 , G06F13/16 , G06F12/121
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
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公开(公告)号：US11481149B2
公开(公告)日：2022-10-25
申请号：US16706078
申请日：2019-12-06
发明人： Sun-Young Lim , Ki-Seok Oh , Sungyong Seo , Youngjin Cho , Insu Choi
IPC分类号： G06F3/06 , G11C14/00 , G11C11/406
摘要： A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.
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公开(公告)号：US11106363B2
公开(公告)日：2021-08-31
申请号：US16414893
申请日：2019-05-17
发明人： Youngjin Cho , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F12/121 , G06F3/06 , G11C16/26 , G11C16/10 , G06F12/0868 , G06F12/0893 , G11C11/00 , G06F13/16
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
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