-
公开(公告)号：US09772900B2
公开(公告)日：2017-09-26
申请号：US14606334
申请日：2015-01-27
发明人： Chaohong Hu , Uksong Kang , Hongzhong Zheng
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/1012 , G06F11/1024 , G06F11/1048 , G06F11/106 , G06F11/108 , G06F2211/1057
摘要： Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.
-
公开(公告)号：US11887650B2
公开(公告)日：2024-01-30
申请号：US18125098
申请日：2023-03-22
发明人： Uksong Kang , Hoiju Chung
IPC分类号： G11C11/40 , G11C11/406 , G11C11/408
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/4087 , G11C11/40618 , G11C11/40622 , G11C11/40626
摘要： A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.
-
公开(公告)号：US20190278487A1
公开(公告)日：2019-09-12
申请号：US16414893
申请日：2019-05-17
发明人： Youngjin CHO , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F3/06 , G06F12/0893 , G11C11/00 , G06F13/16 , G06F12/0868 , G11C16/26 , G11C16/10
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
-
公开(公告)号：US10002043B2
公开(公告)日：2018-06-19
申请号：US14678968
申请日：2015-04-04
发明人： Chaohong Hu , Liang Yin , Hongzhong Zheng , Uksong Kang
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1076
摘要： A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.
-
公开(公告)号：US11614866B2
公开(公告)日：2023-03-28
申请号：US17389834
申请日：2021-07-30
发明人： Youngjin Cho , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F3/06 , G11C16/26 , G11C16/10 , G06F12/0868 , G06F12/0893 , G11C11/00 , G06F13/16 , G06F12/121
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
-
公开(公告)号：US11106363B2
公开(公告)日：2021-08-31
申请号：US16414893
申请日：2019-05-17
发明人： Youngjin Cho , Sungyong Seo , Sun-Young Lim , Uksong Kang , Chankyung Kim , Duckhyun Chang , JinHyeok Choi
IPC分类号： G06F12/121 , G06F3/06 , G11C16/26 , G11C16/10 , G06F12/0868 , G06F12/0893 , G11C11/00 , G06F13/16
摘要： A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
-
公开(公告)号：US10269394B2
公开(公告)日：2019-04-23
申请号：US15820473
申请日：2017-11-22
发明人： Chankyung Kim , Uksong Kang , Nam Sung Kim
摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.
-
公开(公告)号：US10002044B2
公开(公告)日：2018-06-19
申请号：US14678977
申请日：2015-04-04
发明人： Chaohong Hu , Hongzhong Zheng , Uksong Kang , Zhan Ping
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1076
摘要： A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.
-
公开(公告)号：US09971697B2
公开(公告)日：2018-05-15
申请号：US15354354
申请日：2016-11-17
发明人： Chankyung Kim , Uksong Kang , Sanguhn Cha , Sungyong Seo , Youngjin Cho , Seongil O
IPC分类号： G06F12/08 , G06F12/0871 , G11C11/4093 , G11C7/10 , G06F12/0802 , G06F12/0853
CPC分类号： G06F12/0871 , G06F11/1064 , G06F12/0802 , G06F12/0804 , G06F12/0853 , G06F12/0868 , G06F12/0895 , G06F2212/1004 , G06F2212/1028 , G06F2212/205 , G06F2212/214 , G06F2212/22 , G06F2212/313 , G06F2212/60 , G06F2212/601 , G06F2212/7203 , G11C5/04 , G11C7/1072 , G11C11/005 , G11C11/4093 , G11C16/0483
摘要： A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.
-
10.发明授权公开(公告)号：US09847105B2
公开(公告)日：2017-12-19
申请号：US15012845
申请日：2016-02-01
发明人： Chankyung Kim , Uksong Kang , Nam Sung Kim
IPC分类号： G06F12/06 , G11C5/02 , G11C5/06 , G11C11/406
CPC分类号： G11C5/02 , G06F12/0638 , G06F2212/205 , G11C5/025 , G11C5/06 , G11C8/12 , G11C11/40611 , G11C14/0009
摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.023 秒)
