公开(公告)号：US12079080B2

公开(公告)日：2024-09-03

申请号：US18335375

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Heehyun Nam ,  Jeongho Lee ,  Younho Jeon

IPC: H03M13/15 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US20180329651A1

公开(公告)日：2018-11-15

申请号：US15669851

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

公开(公告)号：US12056066B2

公开(公告)日：2024-08-06

申请号：US17466726

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Younho Jeon ,  Daehui Kim ,  Heehyun Nam

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4022

Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.

公开(公告)号：US20230185717A1

公开(公告)日：2023-06-15

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US11983115B2

公开(公告)日：2024-05-14

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US11853215B2

公开(公告)日：2023-12-26

申请号：US17408767

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Heehyun Nam ,  Jeongho Lee

IPC: G06F12/08 ,  G06F12/0806 ,  G06F12/02 ,  G06F12/0862

CPC classification number: G06F12/0806 ,  G06F12/0253 ,  G06F12/0862 ,  G06F2212/1036

Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.

公开(公告)号：US11720442B2

公开(公告)日：2023-08-08

申请号：US17510898

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Heehyun Nam ,  Jeongho Lee ,  Younho Jeon

IPC: H03M13/15 ,  G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US20220121574A1

公开(公告)日：2022-04-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12001683B2

公开(公告)日：2024-06-04

申请号：US18087464

申请日：2022-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyeon Tak ,  Hyunseon Park ,  Heehyun Nam ,  Sumin Ahn ,  Wansoo Choi

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command.

公开(公告)号：US11741034B2

公开(公告)日：2023-08-29

申请号：US17368981

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heehyun Nam ,  Jeongho Lee ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2213/28

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.