公开(公告)号：US11942515B2

公开(公告)日：2024-03-26

申请号：US17725617

申请日：2022-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongki Jung ,  Myungil Kang ,  Yoonhae Kim ,  Kwanheum Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.

公开(公告)号：US20240145544A1

公开(公告)日：2024-05-02

申请号：US18482154

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Kim ,  Myungil Kang ,  Kyunghee Cho ,  Doyoung Choi ,  Donghoon Hwang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78645 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.

公开(公告)号：US20240047539A1

公开(公告)日：2024-02-08

申请号：US17984025

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Mehdi Saremi ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Harsono Simka ,  Sungil Park ,  Myungil Kang ,  Kyungho Kim ,  Doyoung Choi ,  JaeHyun Park

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/41791 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/6681 ,  H01L29/8083

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

公开(公告)号：US10312153B2

公开(公告)日：2019-06-04

申请号：US15914125

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/165 ,  H01L21/8238

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US09559102B2

公开(公告)日：2017-01-31

申请号：US14976105

申请日：2015-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonhae Kim ,  Myungil Kang ,  Sooyeon Jeong

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L27/0922 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/785

Abstract: A semiconductor device includes first and second active regions. Each active region includes a plurality of fin protrusions and a recessed area disposed between the fin protrusions. A plurality of gate structures are disposed on each of the plurality of fin protrusions. A semiconductor layer is disposed in each recessed area. A distance between the gate structures of the first active region is the same as a distance between the gate structures of the second active region, and a height difference between a bottom surface of the semiconductor layer of the first recessed area and a top surface of each of the fin protrusions of the first active region is smaller than a height difference between a bottom surface of the semiconductor layer of the recessed area of the second active region and a top surface of each of the fin protrusions of the second active region.

Abstract translation: 半导体器件包括第一和第二有源区。 每个有源区域包括多个翅片突出部和设置在翅片突出部之间的凹陷区域。 多个栅极结构设置在多个翅片突起中的每一个上。 半导体层设置在每个凹陷区域中。 第一有源区域的栅极结构之间的距离与第二有源区域的栅极结构之间的距离与第一凹入区域的半导体层的底表面和每个第一有源区域的顶表面之间的高度差相同 第一有源区的鳍突起的距离小于第二有源区的凹陷区域的半导体层的底表面和第二有源区的每个鳍突起的顶表面之间的高度差。

公开(公告)号：US09941174B2

公开(公告)日：2018-04-10

申请号：US15007711

申请日：2016-01-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L31/0312 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US09882004B2

公开(公告)日：2018-01-30

申请号：US15423406

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongki Jung ,  Myungil Kang ,  Yoonhae Kim ,  Kwanheum Lee

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.

公开(公告)号：US09691902B2

公开(公告)日：2017-06-27

申请号：US14990398

申请日：2016-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungil Kang ,  Yoonhae Kim ,  Byeongchan Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/785

Abstract: A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.

公开(公告)号：US20240379409A1

公开(公告)日：2024-11-14

申请号：US18535089

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Jeon ,  Wooseok Park ,  Donghoon Hwang ,  Myungil Kang ,  Kyungho Kim ,  Byungho Moon

IPC: H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.

公开(公告)号：US20240321886A1

公开(公告)日：2024-09-26

申请号：US18605400

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Myungil Kang ,  Kyungho Kim ,  Kyowook Lee ,  Seunghun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device includes a plurality of transistors including a pair of pull-up transistors in a first layer, a pair of pull-down transistors in a second layer that is at a different vertical level than the first layer, and a pair of pass-gate transistors in the first or second layer, a contact configured to electrically connect a source/drain region of one of the pull-up transistors, a source/drain region of one of the pull-down transistors, and a source/drain region of one of the pass-gate transistors to one another, a gate contact configured to connect a gate electrode of the other pull-up transistor to a gate electrode of the other pull-down transistor, and an upper wire on the contact and the gate contact, the upper wire extending in a first horizontal direction and being connected to the contact and the gate contact.