公开(公告)号：US20240379409A1

公开(公告)日：2024-11-14

申请号：US18535089

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Jeon ,  Wooseok Park ,  Donghoon Hwang ,  Myungil Kang ,  Kyungho Kim ,  Byungho Moon

IPC: H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.

公开(公告)号：US20250098278A1

公开(公告)日：2025-03-20

申请号：US18815956

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Moon ,  Donghoon Hwang ,  Hyojin Kim ,  Kyunghee Cho

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.

公开(公告)号：US20240162322A1

公开(公告)日：2024-05-16

申请号：US18206139

申请日：2023-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Shin ,  Donghoon Hwang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include an active region on a substrate, channel patterns on the active region, and gate electrodes on the channel patterns, respectively, and extending in a first direction. The channel patterns may include a first subset of the channel patterns, each of which has a first width, and a second subset of the channel patterns, each of which has a second width. The first and second subsets may be adjacent to each other in a second direction. The channel patterns may further include a buffer channel pattern between the first subset and the second subset. The buffer channel pattern may include a connection side surface extending in the first direction, and the connection side surface may be configured such that a width of the buffer channel pattern changes from the first width to the second width when moving from the first subset to the second subset.

公开(公告)号：US20250107178A1

公开(公告)日：2025-03-27

申请号：US18643104

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Donghoon Hwang ,  Hyojin Kim ,  Byungho Moon ,  Doyoung Choi

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.

公开(公告)号：US20240321875A1

公开(公告)日：2024-09-26

申请号：US18603591

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok PARK ,  Jaeho Jeon ,  Donghoon Hwang ,  Taehyun Ryu ,  Namhyun Lee

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a plurality of nanosheet stacks on the active region, a plurality of gate lines extending in a second horizontal direction intersecting the first horizontal direction, on the active region, and surrounding the plurality of nanosheet stacks, and a first insulating pattern between two nanosheet stacks adjacent in the first horizontal direction among the plurality of nanosheet stacks, on the active region, and extending in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, wherein the first insulating pattern is in contact with the plurality of nanosheet stacks.

公开(公告)号：US20240339453A1

公开(公告)日：2024-10-10

申请号：US18544670

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Donghoon Hwang ,  Inchan Hwang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional (3D) semiconductor device includes a substrate including a first surface and a second surface that are opposite to each other, a lower active region on the first surface of the substrate, the lower active region including a lower channel pattern and a lower source/drain pattern that are electrically connected to each other, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source/drain pattern that are electrically connected to each other, a dam pattern that vertically extends from the lower source/drain pattern to the upper source/drain pattern, a lower active contact electrically connected to the lower source/drain pattern, an upper active contact electrically connected to the upper source/drain pattern, and a vertical via that vertically extends along the dam pattern to electrically connect the lower active contact to the upper active contact.

公开(公告)号：US20230411471A1

公开(公告)日：2023-12-21

申请号：US18295867

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Cha ,  Minchan Gwak ,  Donghoon Hwang ,  Sora You ,  Sungmoon Lee

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/41766 ,  H01L27/088 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: A semiconductor device includes first and second active regions on a substrate and extending in a first direction, first and second gate structures on the first and second active regions, respectively, the first and second gate structures extending in a second direction and being spaced apart from each other in the second direction, first and second source/drain regions on the first and second active regions, respectively, and spaced apart from the first and second gate structures, first and second contact plugs on the first and second source/drain regions and respectively connected to the first and second source/drain regions, and a vertical buried structure between the first and second gate structures and between the first and second source/drain regions. The vertical buried structure may include first and second side surfaces, and the first contact plug contacts the first side surface of the vertical buried structure.

公开(公告)号：US20240145544A1

公开(公告)日：2024-05-02

申请号：US18482154

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Kim ,  Myungil Kang ,  Kyunghee Cho ,  Doyoung Choi ,  Donghoon Hwang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78645 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.

公开(公告)号：US10410886B2

公开(公告)日：2019-09-10

申请号：US15602599

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Sangjin Kim ,  Donghoon Hwang ,  Sebeom Oh ,  Yunkyeong Jang

IPC: H01L21/56 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/544 ,  H01L21/308

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a lower mold layer on a substrate that includes first and second regions, forming first and second intermediate mold patterns on the first and second regions, respectively, forming first spacers on sidewalls of the first and second intermediate mold patterns, etching the lower mold layer to form first and second lower mold patterns on the first and second regions, respectively, and etching the substrate to form active patterns and dummy patterns on the first and second regions, respectively. A first distance between a pair of the first intermediate mold patterns may be greater than a second distance between a pair of the second intermediate mold patterns, and the second lower mold patterns may include at least one first merged pattern, whose width is substantially equal to the second distance.