公开(公告)号：US20160380075A1

公开(公告)日：2016-12-29

申请号：US15170230

申请日：2016-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup CHUNG ,  Hyun-Jo KIM ,  Seong-Yul PARK ,  Se-Wan PARK ,  Jong-Mil YOUN ,  Jeong-Hyo LEE ,  Hwa-Sung RHEE ,  Hee-Don JEONG ,  Ji-Yong HA

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L29/66545 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7854 ,  H01L29/7855

Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.

Abstract translation: 半导体器件包括鳍状图案，其包括彼此相对的第一短边和第二短边，与第一短边接触的第一沟槽，与第二短边接触的第二沟槽，第一场绝缘 所述第一场绝缘膜包括从所述第一短边顺序布置的第一部分和第二部分，并且所述第一部分的高度不同于所述第二部分的高度;第二场绝缘膜， 第二沟槽和第一场绝缘膜的第一部分上的第一伪栅极。

公开(公告)号：US20160247925A1

公开(公告)日：2016-08-25

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20160064380A1

公开(公告)日：2016-03-03

申请号：US14934119

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.