公开(公告)号：US11798872B2

公开(公告)日：2023-10-24

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Jeonggi Jin ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US11664312B2

公开(公告)日：2023-05-30

申请号：US17147661

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Seong-Hoon Bae ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US20240234103A1

公开(公告)日：2024-07-11

申请号：US18404423

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334

Abstract: A ring assembly is used in a semiconductor wafer etching device in which a plasma gas flow stream line is not uniform and which surrounds a wafer support plate supporting a semiconductor wafer. The ring assembly includes: an edge ring protruding from at least one side of the semiconductor wafer to have an upper surface higher than an upper surface of the semiconductor wafer; and a shadow ring movable up and down above the edge ring and configured to be tilted with respect to the semiconductor wafer.

公开(公告)号：US20240203888A1

公开(公告)日：2024-06-20

申请号：US18430066

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US20240105680A1

公开(公告)日：2024-03-28

申请号：US18198418

申请日：2023-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung Oh ,  Jumyong Park ,  Dongjoon Oh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08146 ,  H01L2224/16225 ,  H01L2224/48147 ,  H01L2224/48149 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15321

Abstract: A semiconductor chip stack structure includes: a first semiconductor chip including a first semiconductor substrate, a first redistribution layer on the first semiconductor substrate and including a first redistribution pattern, and a first pad on an outermost side of the first redistribution layer; a second semiconductor chip including a second semiconductor substrate, a second redistribution layer on the second semiconductor substrate and including a second redistribution pattern, and a second pad on an outermost side of the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire on the first semiconductor chip; a second metal wire on the second semiconductor chip; and a molding member on the first semiconductor chip and at least a portion of each of the second semiconductor chip, the first metal wire, and the second metal wire.

公开(公告)号：US20240145366A1

公开(公告)日：2024-05-02

申请号：US18141519

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Jumyong Park ,  Solji Song ,  Hyunchul Jung ,  Sanghoo Cho ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/27416 ,  H01L2224/27444 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

公开(公告)号：US20240006288A1

公开(公告)日：2024-01-04

申请号：US18369684

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  JUMYONG PARK ,  JIN HO AN ,  Dongjoon Oh ,  JEONGGI JIN ,  HYUNSU HWANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L23/49816 ,  H01L2225/1058 ,  H01L2224/16235 ,  H01L2924/182 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US11139251B2

公开(公告)日：2021-10-05

申请号：US16592131

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon Oh ,  Sukho Lee ,  Jusuk Kang

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.

公开(公告)号：US12224256B2

公开(公告)日：2025-02-11

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US12009288B2

公开(公告)日：2024-06-11

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.