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    DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME
    1.
    发明申请
    DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230110301A1

    公开(公告)日：2023-04-13

    申请号：US17806827

    申请日：2022-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Junyoung Park ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: H03K5/156 ,  G11C7/22 ,  H03K3/017 ,  H03K5/135

    Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.

    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    4.
    发明公开
    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20240241802A1

    公开(公告)日：2024-07-18

    申请号：US18383350

    申请日：2023-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Park ,  Joohwan Kim ,  Jindo Byun ,  Eunseok Shin ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: G06F11/16 ,  G06F1/10

    CPC classification number: G06F11/1604 ,  G06F1/10 ,  G06F2201/805

    Abstract: The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.

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