知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.022 seconds)

    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    1.
    发明公开
    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20240241802A1

    公开(公告)日：2024-07-18

    申请号：US18383350

    申请日：2023-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Park ,  Joohwan Kim ,  Jindo Byun ,  Eunseok Shin ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: G06F11/16 ,  G06F1/10

    CPC classification number: G06F11/1604 ,  G06F1/10 ,  G06F2201/805

    Abstract: The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.

    Memory package and storage device including the same
    6.
    发明授权
    Memory package and storage device including the same 有权

    公开(公告)号：US11657860B2

    公开(公告)日：2023-05-23

    申请号：US17361780

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joohwan Kim ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/08 ,  G11C7/10 ,  G06F3/06 ,  G11C7/22

    CPC classification number: G11C7/1084 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/222

    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

    Memory device supporting a high-efficient input/output interface and a memory system including the memory device
    9.
    发明授权
    Memory device supporting a high-efficient input/output interface and a memory system including the memory device 有权

    公开(公告)号：US11461251B2

    公开(公告)日：2022-10-04

    申请号：US17326513

    申请日：2021-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin Jin ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

Patent Agency Ranking