公开(公告)号：US20140252544A1

公开(公告)日：2014-09-11

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US20140097535A1

公开(公告)日：2014-04-10

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM INCORPORATED

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/98 ,  H01L23/488

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US09379065B2

公开(公告)日：2016-06-28

申请号：US13969436

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  Zhongping Bao ,  Reynante Tamunan Alvarado

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/58 ,  H01L23/528 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L23/562 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/0231 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06179 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.

Abstract translation: 一些实施方案提供了一种半导体器件（例如，管芯，晶片），其包括衬底，耦合到衬底的金属层和电介质层，耦合到几个金属层中的一个的焊盘，耦合到焊盘的第一金属再分布层， 凸起下金属化（UBM）层，其耦合到第一金属再分配层。 半导体器件包括构造成围绕半导体器件的凸起区域和半导体器件的焊盘区域的几个裂纹停止结构。 凸块区域包括UBM层。 垫区包括垫。 在一些实施方案中，至少一个裂纹停止结构包括第一金属层和第一通孔。 在一些实施方案中，至少一个裂纹停止结构还包括第二金属层，第二通孔和第三金属层。 在一些实施方案中，至少一个裂纹停止结构是倒锥形裂纹停止结构。

公开(公告)号：US09263186B2

公开(公告)日：2016-02-16

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02 ,  H01G2/06 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01G4/38 ,  H01G4/40 ,  H01L23/498

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US08963339B2

公开(公告)日：2015-02-24

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L21/98

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US20150048517A1

公开(公告)日：2015-02-19

申请号：US13969436

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  Zhongping Bao ,  Reynante Tamunan Alvarado

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/0231 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06179 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.

Abstract translation: 一些实施方案提供了一种半导体器件（例如，管芯，晶片），其包括衬底，耦合到衬底的金属层和电介质层，耦合到几个金属层中的一个的焊盘，耦合到焊盘的第一金属再分布层， 凸起下金属化（UBM）层，其耦合到第一金属再分配层。 半导体器件包括构造成围绕半导体器件的凸起区域和半导体器件的焊盘区域的几个裂纹停止结构。 凸块区域包括UBM层。 垫区包括垫。 在一些实施方案中，至少一个裂纹停止结构包括第一金属层和第一通孔。 在一些实施方案中，至少一个裂纹停止结构还包括第二金属层，第二通孔和第三金属层。 在一些实施方案中，至少一个裂纹停止结构是倒锥形裂纹停止结构。

公开(公告)号：US09406649B2

公开(公告)日：2016-08-02

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

公开(公告)号：US20150155265A1

公开(公告)日：2015-06-04

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US08847391B2

公开(公告)日：2014-09-30

申请号：US13777271

申请日：2013-02-26

Applicant: QUALCOMM Incorporated

Inventor： Zhongping Bao ,  Lily Zhao ,  Michael Kim-Kwong Han

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06141 ,  H01L2224/06145 ,  H01L2224/06517 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/14145 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract translation: 本公开的一些示例性实施例涉及包括封装衬底，管芯和耦合到封装衬底和管芯的一组凹凸金属化（UBM）结构的半导体封装。 每个UBM结构沿其相应的横向尺寸具有非圆形横截面。 每个UBM结构包括第一较窄部分和第二较宽部分。 第一较窄部分具有第一宽度。 第二较宽部分具有大于第一宽度的第二宽度。 每个UBM结构朝向模具的特定区域，使得UBM结构的第一较窄部分比UBM结构的第二较宽部分更靠近模具的特定区域。

公开(公告)号：US20140008788A1

公开(公告)日：2014-01-09

申请号：US13777271

申请日：2013-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Zhongping Bao ,  Lily Zhao ,  Michael Han

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06141 ,  H01L2224/06145 ,  H01L2224/06517 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/14145 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract translation: 本公开的一些示例性实施例涉及包括封装衬底，管芯和耦合到封装衬底和管芯的一组凹凸金属化（UBM）结构的半导体封装。 每个UBM结构沿其相应的横向尺寸具有非圆形横截面。 每个UBM结构包括第一较窄部分和第二较宽部分。 第一较窄部分具有第一宽度。 第二较宽部分具有大于第一宽度的第二宽度。 每个UBM结构朝向模具的特定区域，使得UBM结构的第一较窄部分比UBM结构的第二较宽部分更靠近模具的特定区域。