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    Transistor amplifier circuit and integrated circuit
    1.
    发明授权
    Transistor amplifier circuit and integrated circuit 有权

    公开(公告)号：US10043894B2

    公开(公告)日：2018-08-07

    申请号：US14542990

    申请日：2014-11-17

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Tony Vanhoucke ,  Evelyne Gridelet ,  Anco Heringa ,  Jan Willem Slotboom ,  Dirk Klaassen

    IPC: H01L29/737 ,  H01L29/06 ,  H01L29/735 ,  H01L29/78 ,  H01L29/165

    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

    METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT
    3.
    发明申请
    METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT 有权
    加工硅晶圆和硅集成电路的方法

    公开(公告)号：US20140167055A1

    公开(公告)日：2014-06-19

    申请号：US14098923

    申请日：2013-12-06

    Applicant: NXP B.V.

    Inventor： Evelyne Gridelet ,  Hans Mertens ,  Michiel Jos van Duuren ,  Tony Vanhoucke ,  Viet Thanh Dinh

    IPC: H01L21/02 ,  H01L27/06

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/11546

    Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

    Abstract translation: 公开了用于处理硅晶片的方法和系统。 一种方法包括在硅晶片中提供闪速存储区域，并在硅晶片中提供具有多晶硅外部基极的双极晶体管。 闪存区域和双极晶体管通过沉积闪存区域和双极晶体管两者共同的单个多晶硅层来形成。

    Fringe capacitor arranged based on metal layers with a selected orientation of a preferred direction
    4.
    发明授权
    Fringe capacitor arranged based on metal layers with a selected orientation of a preferred direction 有权

    公开(公告)号：US11532546B2

    公开(公告)日：2022-12-20

    申请号：US17239884

    申请日：2021-04-26

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Bartholomeus Wilhelmus Christiaan Hovens ,  Marina Vroubel

    IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08

    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.

    Semiconductor device having a dielectric layer with different thicknesses and method for forming
    5.
    发明授权
    Semiconductor device having a dielectric layer with different thicknesses and method for forming 有权

    公开(公告)号：US10134860B2

    公开(公告)日：2018-11-20

    申请号：US15456963

    申请日：2017-03-13

    Applicant: NXP B.V.

    Inventor： Jan Sonsky ,  Viet Thanh Dinh ,  Jan Claes

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.

    FINFET WITH LOCAL HEATSINKING AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    FINFET WITH LOCAL HEATSINKING AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250157872A1

    公开(公告)日：2025-05-15

    申请号：US18506248

    申请日：2023-11-10

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Asanga H. Perera ,  Sai-Wang Tam

    IPC: H01L23/367 ,  H01L29/66 ,  H01L29/78

    Abstract: One example discloses a finFet semiconductor device and corresponding manufacturing method is disclosed, the device comprising: a substrate having therein a body-region, a plurality of elongate fins at a first major surface and within the body-region; an oxide layer on the first major surface and partially surrounding a lower portion of the elongate fins; a gate contact extending across and partially surrounding an upper portion of the plurality of elongate fins; a dielectric material, between the fins and the gate region; a plurality of elongate partial fins, parallel thereto and having a height which is less than a height thereof; an elongate metal contact, extending into the substrate and in electrical contact with the partial fins, and forming a body-contact; wherein the elongate metal contact extends between the two of the elongate partial fins and below an upper surface thereof and fills a space therebetween.

    FINFET WITH GATE EXTENSION
    10.
    发明公开
    FINFET WITH GATE EXTENSION 审中-公开

    公开(公告)号：US20240014324A1

    公开(公告)日：2024-01-11

    申请号：US17810846

    申请日：2022-07-06

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Asanga H. Perera ,  Arjan Mels

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84

    CPC classification number: H01L29/7856 ,  H01L29/66803 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/845

    Abstract: A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.

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