公开(公告)号：US20250081486A1

公开(公告)日：2025-03-06

申请号：US18458235

申请日：2023-08-30

Applicant: NXP B.V.

Inventor： Ronald Willem Arnoud Werkman ,  Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee

IPC: H01L29/66 ,  H01L29/40

Abstract: A process for making a transistor that includes removing a sacrificial material under a base layer that includes dopants for an intrinsic base of a transistor. After the removal of the sacrificial layer to form a cavity directly under the base layer, a semiconductor material is formed in the cavity. The semiconductor layer includes dopants for a current electrode of the transistor that is located directly under the intrinsic base of the transistor.

公开(公告)号：US20160141357A1

公开(公告)日：2016-05-19

申请号：US14942499

申请日：2015-11-16

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Wilhelmus Cornelis Maria Peters

IPC: H01L29/06 ,  H01L29/36 ,  H01L21/324 ,  H01L21/306 ,  H01L21/225 ,  H01L29/167 ,  H01L49/02

CPC classification number: H01L29/0638 ,  H01L21/2253 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76237 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0684 ,  H01L29/167 ,  H01L29/36

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type. The device also includes an array of interconnected trenches extending into the body region from a surface of the substrate. The device further includes a plurality of channel stoppers. Each channel stopper includes a doped region of the first conductivity type located at a side of one or more of the trenches at a position intermediate a top of the trench and a bottom of the trench.

Abstract translation: 半导体器件及其制造方法。 该器件包括具有第一导电类型的体区的半导体衬底。 该装置还包括从衬底的表面延伸到体区的互连沟槽阵列。 该装置还包括多个通道塞子。 每个通道阻挡件包括位于沟槽顶部和沟槽底部之间的位置处的一个或多个沟槽的一侧的第一导电类型的掺杂区域。

公开(公告)号：US20210257358A1

公开(公告)日：2021-08-19

申请号：US17176875

申请日：2021-02-16

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Mustafa Acar ,  Dominicus Martinus Wilhelmus Leenaerts

IPC: H01L27/082 ,  H01L23/528 ,  H01L29/165 ,  H01L29/737 ,  H03F3/195

Abstract: A semiconductor device is described including a substrate and a plurality of layers. The semiconductor device includes a cascode arrangement of a first bipolar transistor and a second bipolar transistor. A first-bipolar-transistor-collector of the first bipolar transistor and a second-bipolar-transistor-emitter of the second bipolar transistor are at least partially located in a common region in the same layer of the semiconductor device.

公开(公告)号：US20180337250A1

公开(公告)日：2018-11-22

申请号：US15935306

申请日：2018-03-26

Applicant: NXP B.V.

Inventor： Mahmoud Shehab Mohammad Al-Sa'di ,  Petrus Hubertus Cornelis Magnee

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

公开(公告)号：US20160079345A1

公开(公告)日：2016-03-17

申请号：US14852385

申请日：2015-09-11

Applicant: NXP B.V.

Inventor： Tony Vanhoucke ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee ,  Ponky Ivo ,  Dirk Klaassen ,  Mahmoud Shehab Mohammad Al-Sa'di

IPC: H01L29/06 ,  H01L29/66 ,  H03F3/21 ,  H01L29/417 ,  H01L21/324 ,  H01L29/735 ,  H01L29/08

CPC classification number: H01L29/063 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378 ,  H03F3/21

Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

Abstract translation: 一种包括双极晶体管的半导体器件及其制造方法。 一种功率放大器，包括双极晶体管。 双极晶体管包括具有横向延伸漂移区的集电极。 双极晶体管还包括位于集电极之上的基极。 双极晶体管还包括位于基极上方的发射极。 双极晶体管还包括具有不同于集电极的导电类型的掺杂区域。 掺杂区域在集电极下方横向延伸以在掺杂区域和集电极之间的接触区域处形成结。 掺杂区域具有非均匀的横向掺杂分布。 在最接近双极晶体管的集电极 - 基极结的掺杂区域的一部分中，掺杂区域的掺杂水平最高。

公开(公告)号：US11990536B2

公开(公告)日：2024-05-21

申请号：US17646716

申请日：2021-12-31

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Ronald Willem Arnoud Werkman

IPC: H01L29/737 ,  H01L27/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/66242

Abstract: A semiconductor device and fabrication method are described for manufacturing a heterojunction bipolar transistor by forming a silicon collector region in a substrate which includes a lower collector layer, a dopant diffusion barrier layer, and an upper collector layer, where the formation of the dopant diffusion barrier layer reduces diffusion of dopants from the lower collector layer into the upper collector layer during one or more subsequent manufacturing steps which are used to form a trench isolation region in the substrate along with a heterogeneous base region and a silicon emitter region.

公开(公告)号：US20200075585A1

公开(公告)日：2020-03-05

申请号：US16120098

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Pieter Simon van Dijk ,  Johannes Josephus Theodorus Marinus Donkers ,  Dolphin Abessolo Bidzo

IPC: H01L27/082 ,  H01L21/8222 ,  H01L21/8249 ,  H01L21/02 ,  H01L21/306 ,  H01L21/266 ,  H01L21/225 ,  H01L21/324 ,  H01L27/02 ,  H01L27/06 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.

公开(公告)号：US10566423B2

公开(公告)日：2020-02-18

申请号：US15396558

申请日：2016-12-31

Applicant: NXP B.V.

Inventor： Mahmoud Shehab Mohammad Al-Sa'di ,  Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Ihor Brunets ,  Anurag Vohra ,  Jan Willem Slotboom

IPC: H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor switch device for switching an RF signal and a method of making the same. The device includes a first semiconductor region having a first conductivity type. The device also includes a source region and a drain region located in the first semiconductor region. The source region and the drain region have a second conductivity type. The second conductivity type is different to the first conductivity type. The device further includes a gate separating the source region from the drain region. The device also includes at least one sinker region having the second conductivity type. Each sinker region is connectable to an external potential for drawing minority carriers away from the source and drain regions to reduce a leakage current at junctions between the source and drain regions and the first semiconductor region.

公开(公告)号：US09484398B2

公开(公告)日：2016-11-01

申请号：US14925205

申请日：2015-10-28

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Patrick Sebel

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/31 ,  H01L21/3213 ,  H01L23/538 ,  H01L27/06 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/7687 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack.

Abstract translation: 公开了一种金属绝缘体金属，MIM，电容器。 MIM电容器包括形成在互连金属层内的MIM堆叠。 互连金属层用作与MIM堆叠的金属层的电连接。

公开(公告)号：US20140162426A1

公开(公告)日：2014-06-12

申请号：US14177880

申请日：2014-02-11

Applicant: NXP B.V.

Inventor： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

IPC: H01L29/732

CPC classification number: H01L29/732 ,  H01L29/66242 ,  H01L29/7378

Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.