公开(公告)号：US11652107B2

公开(公告)日：2023-05-16

申请号：US16447874

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Nicholas Thomson ,  Ayan Kar ,  Kalyan Kolluru ,  Nathan Jack ,  Rui Ma ,  Mark Bohr ,  Rishabh Mehandru ,  Halady Arpit Rao

IPC: H01L29/06 ,  H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L29/861

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/1211 ,  H01L29/8613

Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

公开(公告)号：US11652060B2

公开(公告)日：2023-05-16

申请号：US16236228

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Rajabali Koduri ,  Leonard Neiberg ,  Altug Koker ,  Swaminathan Sivakumar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/78 ,  H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/78 ,  H01L22/20 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/73209

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

公开(公告)号：US11563081B2

公开(公告)日：2023-01-24

申请号：US17000729

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8234

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US11373999B2

公开(公告)日：2022-06-28

申请号：US16002723

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Rishabh Mehandru ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Mark Bohr ,  Marni Nabors

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US10249588B2

公开(公告)日：2019-04-02

申请号：US15369815

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Valery M. Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/48

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

公开(公告)号：US11749663B2

公开(公告)日：2023-09-05

申请号：US17742205

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Glenn J. Hinton ,  Rajesh Kumar

IPC: H01L21/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US11462536B2

公开(公告)日：2022-10-04

申请号：US16147538

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Anupama Bowonder ,  Rishabh Mehandru ,  Mark Bohr ,  Tahir Ghani

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.

公开(公告)号：US11201129B2

公开(公告)日：2021-12-14

申请号：US16283582

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Valery M. Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/48

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

公开(公告)号：US20200058646A1

公开(公告)日：2020-02-20

申请号：US16103809

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Brian S. Doyle

IPC: H01L27/06 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11 ,  H01L23/522

Abstract: Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

公开(公告)号：US11978727B2

公开(公告)日：2024-05-07

申请号：US16641922

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Doug Ingerly ,  Robert Sankman ,  Mark Bohr ,  Debendra Mallik

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.