公开(公告)号：US20230317140A1

公开(公告)日：2023-10-05

申请号：US17708448

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Rajabali Koduri ,  Pushkar Ranade ,  Wilfred Gomes

IPC: G11C11/408 ,  G11C11/4094 ,  H03K19/17728 ,  H03K19/0185

CPC classification number: G11C11/4087 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/17728 ,  H03K19/018521

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

公开(公告)号：US20230186545A1

公开(公告)日：2023-06-15

申请号：US17551647

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss ,  Rajabali Koduri

IPC: G06T15/00 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

CPC classification number: G06T15/005 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

Abstract: Described herein is a cloud-based gaming system in which multiple views of a spectated E-sports event can be rendered and combined into an immersive video having at least three degrees of freedom. Low-latency generation of the immersive video is facilitated via the use of GPU-controlled non-volatile memory on which rendered data for multiple viewpoints are stored.

公开(公告)号：US20230317794A1

公开(公告)日：2023-10-05

申请号：US17712057

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade ,  Rajabali Koduri

IPC: H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/427

CPC classification number: H01L29/1037 ,  H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/66795 ,  H01L23/427 ,  H01L29/247

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

公开(公告)号：US11652060B2

公开(公告)日：2023-05-16

申请号：US16236228

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Rajabali Koduri ,  Leonard Neiberg ,  Altug Koker ,  Swaminathan Sivakumar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/78 ,  H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/78 ,  H01L22/20 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/73209

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

公开(公告)号：US11957974B2

公开(公告)日：2024-04-16

申请号：US17168299

申请日：2021-02-05

Applicant: Intel Corporation

Inventor： Makarand Dharmapurikar ,  Rajabali Koduri ,  Vijay Bahirji ,  Toby Opferman ,  Scott G. Christian ,  Rajeev Penmatsa ,  Selvakumar Panneer

IPC: A63F13/355

CPC classification number: A63F13/355

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

公开(公告)号：US20230317605A1

公开(公告)日：2023-10-05

申请号：US17711917

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Pushkar Ranade ,  Sagar Suthram ,  Rajabali Koduri

IPC: H01L23/528 ,  H01L27/092 ,  H01L23/46 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L23/5283 ,  H01L27/092 ,  H01L23/46 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53276 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/823871

Abstract: Systems and techniques related to narrow interconnects for integrated circuits. An integrated circuit die includes narrow interconnect lines with a relatively high pitch. A system includes an integrated circuit die with narrow interconnect lines and cooling structure to lower an operating temperature of at least the interconnects to a point where conductance of the narrow interconnect is sufficient.

公开(公告)号：US20230317558A1

公开(公告)日：2023-10-05

申请号：US17711848

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani ,  Jack Kavalieros ,  Rajabali Koduri

IPC: H01L23/473 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L23/473 ,  H01L29/42392 ,  H01L29/0673

Abstract: Integrated circuit dies, systems, and techniques are described related to multiple transistor epitaxial layer source and drain transistor circuits operable at low temperatures. A system includes an integrated circuit die having a number of transistors each having a crystalline channel structure, a first layer epitaxial to the channel structure, and a second layer epitaxial to the first layer. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

公开(公告)号：US20230317146A1

公开(公告)日：2023-10-05

申请号：US17711906

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Rajabali Koduri ,  Pushkar Ranade ,  Sagar Suthram

IPC: G11C11/412 ,  H01L27/11

CPC classification number: G11C11/412 ,  H01L27/1108 ,  H01L27/1116

Abstract: Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.

公开(公告)号：US20240008239A1

公开(公告)日：2024-01-04

申请号：US17856870

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy ,  Rajabali Koduri ,  Clifford Ong ,  Sagar Suthram

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

公开(公告)号：US20230418508A1

公开(公告)日：2023-12-28

申请号：US17850090

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Sagar Suthram ,  Wilfred Gomes ,  Rajabali Koduri

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/067

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.