Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.