Invention Grant
- Patent Title: Designs and methods for conductive bumps
-
Application No.: US15369815Application Date: 2016-12-05
-
Publication No.: US10249588B2Publication Date: 2019-04-02
- Inventor: Valery M. Dubin , Sridhar Balakrishnan , Mark Bohr
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/288 ; H01L21/48

Abstract:
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
Public/Granted literature
- US20170084564A1 DESIGNS AND METHODS FOR CONDUCTIVE BUMPS Public/Granted day:2017-03-23
Information query
IPC分类: