公开(公告)号：US20160233361A1

公开(公告)日：2016-08-11

申请号：US15093255

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEITH E. FOGEL ,  JEEHWAN KIM ,  JAE-WOONG NAH ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/035227 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/0352 ,  H01L31/1804 ,  Y02E10/50

Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

公开(公告)号：US20150280023A1

公开(公告)日：2015-10-01

申请号：US14723095

申请日：2015-05-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHRISTOS DIMITRAKOPOULOS ,  AUGUSTIN J. HONG ,  JEEHWAN KIM ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU

IPC: H01L31/0236

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0689 ,  G06F11/0727 ,  G06F11/1076 ,  G06F12/02 ,  H01L31/02366 ,  H04L67/1002 ,  H04W8/04 ,  H04W8/065 ,  Y02E10/50

Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.

Abstract translation: 一种制造光伏器件的方法包括在基片上涂布二嵌段共聚物层，并从二嵌段共聚物层除去第一聚合物材料以形成多个分布孔。 图案形成层沉积在二嵌段共聚物层的剩余表面上和与基材接触的孔中。 剥离二嵌段共聚物层，使图案形成层的一部分与基板保持接触。 使用图案形成层蚀刻衬底以保护衬底的部分以在衬底中形成柱，使得柱在光伏器件中提供辐射吸收结构。

公开(公告)号：US20160072002A1

公开(公告)日：2016-03-10

申请号：US14944741

申请日：2015-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEITH E. FOGEL ,  JEEHWAN KIM ,  JAE-WOONG NAH ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU

IPC: H01L31/18 ,  H01L31/0236 ,  H01L31/0352

CPC classification number: H01L31/035227 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/0352 ,  H01L31/1804 ,  Y02E10/50

Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

Abstract translation: 光电器件和方法包括在衬底层上沉积金属膜。 金属膜退火以在基底层上形成金属膜岛。 使用岛作为蚀刻掩模蚀刻衬底层，以在衬底层中形成柱。

公开(公告)号：US20150140831A1

公开(公告)日：2015-05-21

申请号：US14592421

申请日：2015-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： STEPHEN W. BEDELL ,  CHENG-WEI CHENG ,  DEVENDRA K. SADANA ,  KATHERINE L. SAENGER ,  KUEN-TING SHIU

IPC: H01L21/78 ,  H01L21/02

CPC classification number: H01L21/7813 ,  H01L21/02109 ,  H01L21/02323 ,  H01L21/306

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract translation: 用于分离转移层的方法包括在基板上形成裂纹引导层并在裂纹引导层上形成器件层。 通过将裂纹引导层暴露于减少在与裂纹引导层相邻的界面处的附着力的气体，裂纹引导层被削弱。 在器件层上形成应力诱导层，以帮助通过裂纹引导层和/或界面引发裂纹。 通过传播裂纹将器件层从衬底移除。

公开(公告)号：US20170179237A1

公开(公告)日：2017-06-22

申请号：US15443087

申请日：2017-02-27

Applicant: International Business Machines Corporation

Inventor： CHENG-WEI CHENG ,  EDWARD WILLIAM KIEWRA ,  AMLAN MAJUMDAR ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/20 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78681

Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

公开(公告)号：US20140264446A1

公开(公告)日：2014-09-18

申请号：US13967102

申请日：2013-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ANIRBAN BASU ,  CHENG-WEI CHENG ,  AMLAN MAJUMDAR ,  RYAN M. MARTIN ,  UZMA RANA ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

Abstract translation: 一种用于形成鳍状场效应晶体管的方法，包括在硅衬底上形成电介质层，在电介质层中形成高达纵横比的沟槽直至衬底，高纵横比包括大于或等于1:1的高宽比;以及 使用纵横比捕获工艺在沟槽中外延生长含硅的半导体材料以形成翅片。 蚀刻一个或多个电介质层以暴露鳍片的一部分。 在翅片的一部分上外延生长阻挡层，在鳍片上方形成栅叠层。 围绕翅片和门叠层的部分形成间隔件。 将掺杂剂植入翅片的部分。 源极和漏极区域使用非含硅半导体材料生长在翅片上。

公开(公告)号：US20140220766A1

公开(公告)日：2014-08-07

申请号：US13966931

申请日：2013-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei CHENG ,  JACK O. CHU ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L21/02

CPC classification number: H01L29/267 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/28575 ,  H01L21/3228 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

公开(公告)号：US20180006180A1

公开(公告)日：2018-01-04

申请号：US15705905

申请日：2017-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： STEPHEN W. BEDELL ,  CHENG-WEI CHENG ,  JEEHWAN KIM ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  NORMA E. SOSA CORTES

IPC: H01L31/0687 ,  H01L31/18

Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.

公开(公告)号：US20170179238A1

公开(公告)日：2017-06-22

申请号：US14974019

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： CHENG-WEI CHENG ,  EDWARD WILLIAM KIEWRA ,  AMLAN MAJUMDAR ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/20 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78681

Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

公开(公告)号：US20170162387A1

公开(公告)日：2017-06-08

申请号：US15177495

申请日：2016-06-09

Applicant: International Business Machines Corporation

Inventor： CHENG-WEI CHENG ,  SANGHOON LEE ,  KUEN-TING SHIU

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L21/02491 ,  H01L21/02381 ,  H01L21/02436 ,  H01L21/02463 ,  H01L21/02496 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823431 ,  H01L21/8252 ,  H01L27/0886 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.