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公开(公告)号:US20220407000A1
公开(公告)日:2022-12-22
申请号:US17349359
申请日:2021-06-16
Inventor: Chih-Hsiang YANG , Hsiang-Lan LUNG , Wei-Chih CHIEN , Cheng-Wei CHENG , Matthew J. BRIGHTSKY
Abstract: A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.
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公开(公告)号:US20220123209A1
公开(公告)日:2022-04-21
申请号:US17072906
申请日:2020-10-16
Inventor: Huai-Yu CHENG , I-Ting KUO , Hsiang-Lan LUNG , Cheng-Wei CHENG , Matthew J. BRIGHTSKY
Abstract: A switching device having a first electrode, a second electrode, and a switching layer between the first and second electrodes, formed using a chalcogenide composition doped with an element that suppresses oxidation, which results in improved manufacturability and yield. For selector material based on AsSeGeSi or other chalcogenide materials that include selenium or arsenic, or other chalcogenide materials that include selenium or arsenic and silicon, the element added to suppress oxidation can be sulfur.
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公开(公告)号:US20200381250A1
公开(公告)日:2020-12-03
申请号:US16424830
申请日:2019-05-29
Applicant: International Business Machines Corporation
Inventor: Hiroyuki MIYAZOE , Cheng-Wei CHENG , Sanghoon LEE
IPC: H01L21/02 , H01L21/311 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786 , C30B25/04 , C30B25/18 , C30B29/40
Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.
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公开(公告)号:US20140220766A1
公开(公告)日:2014-08-07
申请号:US13966931
申请日:2013-08-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Cheng-Wei CHENG , JACK O. CHU , DEVENDRA K. SADANA , KUEN-TING SHIU , YANNING SUN
IPC: H01L21/02
CPC classification number: H01L29/267 , H01L21/02387 , H01L21/02439 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02661 , H01L21/02664 , H01L21/28575 , H01L21/3228 , H01L29/452 , H01L29/66522 , H01L29/772 , H01L29/78
Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.
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