公开(公告)号：US20170179238A1

公开(公告)日：2017-06-22

申请号：US14974019

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： CHENG-WEI CHENG ,  EDWARD WILLIAM KIEWRA ,  AMLAN MAJUMDAR ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/20 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78681

Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

公开(公告)号：US20170179237A1

公开(公告)日：2017-06-22

申请号：US15443087

申请日：2017-02-27

Applicant: International Business Machines Corporation

Inventor： CHENG-WEI CHENG ,  EDWARD WILLIAM KIEWRA ,  AMLAN MAJUMDAR ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/20 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78681

Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

公开(公告)号：US20140264446A1

公开(公告)日：2014-09-18

申请号：US13967102

申请日：2013-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ANIRBAN BASU ,  CHENG-WEI CHENG ,  AMLAN MAJUMDAR ,  RYAN M. MARTIN ,  UZMA RANA ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU ,  YANNING SUN

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

Abstract translation: 一种用于形成鳍状场效应晶体管的方法，包括在硅衬底上形成电介质层，在电介质层中形成高达纵横比的沟槽直至衬底，高纵横比包括大于或等于1:1的高宽比;以及 使用纵横比捕获工艺在沟槽中外延生长含硅的半导体材料以形成翅片。 蚀刻一个或多个电介质层以暴露鳍片的一部分。 在翅片的一部分上外延生长阻挡层，在鳍片上方形成栅叠层。 围绕翅片和门叠层的部分形成间隔件。 将掺杂剂植入翅片的部分。 源极和漏极区域使用非含硅半导体材料生长在翅片上。

公开(公告)号：US20170148896A1

公开(公告)日：2017-05-25

申请号：US15426566

申请日：2017-02-07

Applicant: International Business Machines Corporation

Inventor： ANIRBAN BASU ,  GUY COHEN ,  AMLAN MAJUMDAR

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/201 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

公开(公告)号：US20160133750A1

公开(公告)日：2016-05-12

申请号：US14982687

申请日：2015-12-29

Applicant: International Business Machines Corporation

Inventor： ANIRBAN BASU ,  GUY COHEN ,  AMLAN MAJUMDAR

IPC: H01L29/78 ,  H01L29/205 ,  H01L29/778 ,  H01L29/201

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.