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    Chip Package Structure And Packaging Method
    1.
    发明申请
    Chip Package Structure And Packaging Method 审中-公开

    公开(公告)号：US20190273044A1

    公开(公告)日：2019-09-05

    申请号：US16415587

    申请日：2019-05-17

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： HuiLi FU ,  Heng LI ,  Xiaodong ZHANG

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

    Abstract: Example chip package structure and packaging methods are described. One example chip package structure includes: a redistribution layer (RDL) and a target chip including an active surface and a back surface, where the active surface of the target chip is connected to a first surface of the RDL. The example chip package structure further includes a substrate, where a first surface of the substrate is opposite to the back surface of the target chip. The example chip package structure further includes an interconnection channel that is located around the target chip. One end of the interconnection channel is connected to the first surface of the RDL, and the other end of the interconnection channel is connected to the first surface of the substrate.

    CHIP AND PACKAGING METHOD
    3.
    发明申请
    CHIP AND PACKAGING METHOD 审中-公开

    公开(公告)号：US20200381361A1

    公开(公告)日：2020-12-03

    申请号：US16997003

    申请日：2020-08-19

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Nan ZHAO ,  Wenxu XIE ,  Junlei TAO ,  Shanghsuan CHIANG ,  HuiLi FU

    IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

    ANTENNA-IN-PACKAGE STRUCTURE AND TERMINAL
    4.
    发明申请
    ANTENNA-IN-PACKAGE STRUCTURE AND TERMINAL 审中-公开

    公开(公告)号：US20200161766A1

    公开(公告)日：2020-05-21

    申请号：US16685621

    申请日：2019-11-15

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Liangsheng LIU ,  Xinhong LI ,  HuiLi FU

    IPC: H01Q9/04 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q23/00 ,  H01Q13/10

    Abstract: The disclosure discloses an antenna-in-package structure, including a first substrate and a second substrate. A first surface of the first substrate includes a first patch antenna, the second substrate is connected to a second surface of the first substrate, and the second substrate is provided with a third surface and a fourth surface. The third surface includes a second patch antenna, and a projection of the second patch antenna on the first surface at least partially overlaps the first patch antenna. A cavity is disposed between the first substrate and the second substrate, and the second patch antenna is separated from the second surface by the cavity. The fourth surface includes a radio frequency element, and the radio frequency element sends and receives a radio frequency signal by using the first patch antenna and the second patch antenna.

    Chip Packaging System
    5.
    发明申请
    Chip Packaging System 审中-公开

    公开(公告)号：US20180247880A1

    公开(公告)日：2018-08-30

    申请号：US15907598

    申请日：2018-02-28

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： HuiLi FU ,  Xing FU ,  Shujie CAI ,  Xiangxiong ZHANG

    IPC: H01L23/38 ,  H01L23/367

    CPC classification number: H01L23/38 ,  H01L23/3675

    Abstract: This application provides a chip packaging system, including multiple chips, a substrate, a heat dissipating component, and at least one thermoelectric refrigeration chip. A heat dissipating ring and a heat dissipating lid are provided on the heat dissipating component. One end of the heat dissipating ring is secured to the substrate, and the other end, opposite to the end secured to the substrate. The multiple chips are disposed in space enclosed by the substrate, the heat dissipating ring, and the heat dissipating lid, and all of the multiple chips are separated each other by using a thermal insulation material or by air. One surface of each of the at least one thermoelectric refrigeration chip is a hot end and the other surface thereof is a cold end. The cold end of each thermoelectric refrigeration chip is disposed on a side close to the multiple chips.

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