公开(公告)号：US20180068922A1

公开(公告)日：2018-03-08

申请号：US15797549

申请日：2017-10-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： HuiLi FU ,  Shujie CAI ,  Feiyu LUO

IPC: H01L23/367 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/367 ,  H01L21/02107 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

公开(公告)号：US20220084849A1

公开(公告)日：2022-03-17

申请号：US17533632

申请日：2021-11-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chao MA ,  Yan LI ,  Wenkai FAN ,  Shujie CAI

IPC: H01L21/67 ,  H05K5/02

Abstract: The technology of this disclosure relates to a chip packaging apparatus. The chip packaging apparatus includes a first differential pin pair, a first pin, and a second pin. The first differential pin pair includes a first differential signal pin and a second differential signal pin. In addition, the first pin and the second pin are both located between the first differential signal pin and the second differential signal pin, and the first pin and the second pin are differential signal pins (or both are power pins). The first pin is adjacent to the first differential signal pin and the second differential signal pin. The second pin is adjacent to the first differential signal pin and the second differential signal pin. The first pin and the second pin are respectively located on two sides of a first imaginary straight line connecting the first differential signal pin to the second differential signal pin.

公开(公告)号：US20180247880A1

公开(公告)日：2018-08-30

申请号：US15907598

申请日：2018-02-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： HuiLi FU ,  Xing FU ,  Shujie CAI ,  Xiangxiong ZHANG

IPC: H01L23/38 ,  H01L23/367

CPC classification number: H01L23/38 ,  H01L23/3675

Abstract: This application provides a chip packaging system, including multiple chips, a substrate, a heat dissipating component, and at least one thermoelectric refrigeration chip. A heat dissipating ring and a heat dissipating lid are provided on the heat dissipating component. One end of the heat dissipating ring is secured to the substrate, and the other end, opposite to the end secured to the substrate. The multiple chips are disposed in space enclosed by the substrate, the heat dissipating ring, and the heat dissipating lid, and all of the multiple chips are separated each other by using a thermal insulation material or by air. One surface of each of the at least one thermoelectric refrigeration chip is a hot end and the other surface thereof is a cold end. The cold end of each thermoelectric refrigeration chip is disposed on a side close to the multiple chips.