公开(公告)号：US20240363604A1

公开(公告)日：2024-10-31

申请号：US18432387

申请日：2024-02-05

申请人： pSemi Corporation

发明人： David GIULIANO

IPC分类号： H01L25/16 ,  H01L23/48 ,  H01L23/522 ,  H01L23/64 ,  H01L27/01 ,  H01L27/06 ,  H02M3/07 ,  H05K1/02 ,  H05K1/11 ,  H10N19/00

CPC分类号： H01L25/16 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/642 ,  H01L27/016 ,  H01L27/0688 ,  H01L28/40 ,  H01L28/90 ,  H02M3/07 ,  H05K1/0298 ,  H05K1/115 ,  H10N19/00 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H02M3/077

摘要： This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

公开(公告)号：US20240363554A1

公开(公告)日：2024-10-31

申请号：US18768084

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chia-Ping Lai

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/585 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2224/80001 ,  H01L2225/06541

摘要： A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

公开(公告)号：US20240363496A1

公开(公告)日：2024-10-31

申请号：US18771120

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/08146

摘要： A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

公开(公告)号：US20240363495A1

公开(公告)日：2024-10-31

申请号：US18767848

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Jung CHEN ,  Cheng-Hung WANG ,  Tsung-Lin LEE ,  Shiuan-Jeng LIN ,  Chun-Ming LIN ,  Wen-Chih CHIANG

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC分类号： H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

摘要： Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20240363494A1

公开(公告)日：2024-10-31

申请号：US18765069

申请日：2024-07-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： LIANG-PIN CHOU

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/53238

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

公开(公告)号：US20240363492A1

公开(公告)日：2024-10-31

申请号：US18307549

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yang-Hsin SHIH ,  Mao-Nan WANG ,  Chih-Hsin YANG ,  Liang-Wei WANG

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/66545

摘要： Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial gate structures are formed concurrently with active gate structures, the sacrificial gate structures being disposed in a through via region of the substrate. The sacrificial gate structures are subsequently removed from the substrate and dielectric material formed in their place. The through substrate via extends through the dielectric material.

公开(公告)号：US12131786B2

公开(公告)日：2024-10-29

申请号：US18104228

申请日：2023-01-31

申请人： Silicon Storage Technology, Inc.

发明人： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC分类号： G11C5/06 ,  G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC分类号： G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

摘要： A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US20240357825A1

公开(公告)日：2024-10-24

申请号：US18760980

申请日：2024-07-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC分类号： H10B43/50 ,  H01L23/48 ,  H10B43/27

CPC分类号： H10B43/50 ,  H01L23/481 ,  H10B43/27

摘要： A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US20240355782A1

公开(公告)日：2024-10-24

申请号：US18756525

申请日：2024-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC分类号： H01L25/065 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L22/32 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

摘要： In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US20240355706A1

公开(公告)日：2024-10-24

申请号：US18302987

申请日：2023-04-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Wei TSAI

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06541

摘要： A method for forming a semiconductor device is provided. The method includes forming a first device layer on a first substrate, forming a dielectric structure on the first device layer, forming a second device layer on the dielectric structure, wherein the first device layer and the second device layer are disposed on opposite sides of the dielectric structure. After the second device layer is formed on the dielectric structure, the method further includes forming a first interconnect structure on the second device layer, removing the first substrate to expose the first device layer, forming vias through the dielectric structure. After the vias are formed, the method further includes forming a second interconnect structure on the first device layer. The vias are electrically connected to both the first interconnect structure and the second interconnect structure.