公开(公告)号：US20230360946A1

公开(公告)日：2023-11-09

申请号：US17738182

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsin YANG ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L24/80 ,  H01L24/05 ,  H01L24/08 ,  H01L24/03 ,  H01L2221/68381 ,  H01L2224/80006 ,  H01L2224/80379 ,  H01L2224/808 ,  H01L2224/03622 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05655 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L28/87

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

公开(公告)号：US20240397830A1

公开(公告)日：2024-11-28

申请号：US18790049

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsin YANG ,  Dian-Hau CHEN ,  Yen-Ming CHEN ,  Yu-Jen WANG ,  Chen-Chiu HUANG

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.

公开(公告)号：US20240363492A1

公开(公告)日：2024-10-31

申请号：US18307549

申请日：2023-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yang-Hsin SHIH ,  Mao-Nan WANG ,  Chih-Hsin YANG ,  Liang-Wei WANG

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/66545

Abstract: Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial gate structures are formed concurrently with active gate structures, the sacrificial gate structures being disposed in a through via region of the substrate. The sacrificial gate structures are subsequently removed from the substrate and dielectric material formed in their place. The through substrate via extends through the dielectric material.

公开(公告)号：US20220328759A1

公开(公告)日：2022-10-13

申请号：US17489352

申请日：2021-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Hsin YANG ,  Dian-Hau CHEN ,  Yen-Ming CHEN ,  Yu-Jen WANG ,  Chen-Chiu HUANG

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.