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公开(公告)号：US20210151668A1
公开(公告)日：2021-05-20
申请号：US17140790
申请日：2021-01-04
Inventor： Yi YANG , Dongna SHEN , Yu-Jen WANG
Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
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公开(公告)号：US20240234401A9
公开(公告)日：2024-07-11
申请号：US18302466
申请日：2023-04-18
Inventor： Chien Hung LIU , Yu-Sheng CHEN , Yi Ching ONG , Hsien Jung CHEN , Kuen-Yi CHEN , Kuo-Ching HUANG , Harry-HakLay CHUANG , Wei-Cheng WU , Yu-Jen WANG
IPC: H01L25/18 , H01L23/00 , H01L23/48 , H01L23/522
CPC classification number: H01L25/18 , H01L23/481 , H01L23/5227 , H01L24/08 , H01L28/40 , H01L2224/08145
Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
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公开(公告)号：US20240136346A1
公开(公告)日：2024-04-25
申请号：US18302466
申请日：2023-04-17
Inventor： Chien Hung LIU , Yu-Sheng CHEN , Yi Ching ONG , Hsien Jung CHEN , Kuen-Yi CHEN , Kuo-Ching HUANG , Harry-HakLay CHUANG , Wei-Cheng WU , Yu-Jen WANG
IPC: H01L25/18 , H01L23/00 , H01L23/48 , H01L23/522
CPC classification number: H01L25/18 , H01L23/481 , H01L23/5227 , H01L24/08 , H01L28/40 , H01L2224/08145
Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
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公开(公告)号：US20220367793A1
公开(公告)日：2022-11-17
申请号：US17816035
申请日：2022-07-29
Inventor： Yi YANG , Dongna SHEN , Vignesh SUNDAR , Yu-Jen WANG
Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
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Patent Agency Ranking
公开(公告)号：US20230420473A1
公开(公告)日：2023-12-28
申请号：US17850477
申请日：2022-06-27
Inventor： Kai-Yun YANG , Yu-Jen WANG
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14685
Abstract: A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.
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公开(公告)号：US20230223063A1
公开(公告)日：2023-07-13
申请号：US17571945
申请日：2022-01-10
Inventor： Chih-Chuan SU , Yu-Jen WANG , Liang-Wei WANG , Dian-Hau CHEN
CPC classification number: G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.
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公开(公告)号：US20240397830A1
公开(公告)日：2024-11-28
申请号：US18790049
申请日：2024-07-31
Inventor： Chih-Hsin YANG , Dian-Hau CHEN , Yen-Ming CHEN , Yu-Jen WANG , Chen-Chiu HUANG
Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.
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公开(公告)号：US20230292629A1
公开(公告)日：2023-09-14
申请号：US17690613
申请日：2022-03-09
Inventor： Tzu-Ting LIU , Yu-Jen WANG , Chih-Pin CHIU , Hung-Chao KAO , Chih-Chuan SU , Liang-Wei WANG , Chen-Chiu HUANG , Dian-Hau CHEN
CPC classification number: H01L43/02 , H01L27/222 , H01L43/12
Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.
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公开(公告)号：US20220328759A1
公开(公告)日：2022-10-13
申请号：US17489352
申请日：2021-09-29
Inventor： Chih-Hsin YANG , Dian-Hau CHEN , Yen-Ming CHEN , Yu-Jen WANG , Chen-Chiu HUANG
Abstract: In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.
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