公开(公告)号：US20240347433A1

公开(公告)日：2024-10-17

申请号：US18630516

申请日：2024-04-09

申请人： SILICON BOX PTE. LTD.

发明人： Sehat SUTARDJA

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/60 ,  H01L2021/6024

摘要： Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.

公开(公告)号：US20240332112A1

公开(公告)日：2024-10-03

申请号：US18744108

申请日：2024-06-14

申请人： Intel Corporation

发明人： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC分类号： H01L23/36 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488

CPC分类号： H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

摘要： An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US12107051B2

公开(公告)日：2024-10-01

申请号：US18230829

申请日：2023-08-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L23/5384 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L21/568 ,  H01L2021/6006 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2224/19 ,  H01L2224/83005

摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20240321622A1

公开(公告)日：2024-09-26

申请号：US18474455

申请日：2023-09-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： YOUNG-JA KIM

IPC分类号： H01L21/683 ,  H01L21/60

CPC分类号： H01L21/6838 ,  H01L21/60 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

摘要： An adsorption device for a reflow process according to an embodiment is coupled to a semiconductor package to form a reflow assembly in a reflow process. The semiconductor package includes a substrate and a semiconductor chip disposed at one surface of the substrate. The adsorption device for the reflow process includes a main body and a pressure control member. The main body includes an inner space portion and includes a bottom portion and a substrate adsorption portion that protrudes from the bottom portion to be adhered to the one surface of the substrate in an outer region of the semiconductor chip by a negative pressure. The pressure control member maintains a pressure of the inner space portion.

公开(公告)号：US20240282755A1

公开(公告)日：2024-08-22

申请号：US18649297

申请日：2024-04-29

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49827 ,  H01L2021/60037

摘要： A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

公开(公告)号：US20240282594A1

公开(公告)日：2024-08-22

申请号：US18564807

申请日：2022-02-21

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Tadashi MAEDA ,  Shingo OKAMURA ,  Yuki YOSHIOKA ,  Tadahiko SAKAI

IPC分类号： H01L21/60

CPC分类号： H01L21/60 ,  H01L2021/6006

摘要： A disclosed method for manufacturing an electronic-component-mounted substrate includes: a step (i) of forming a temporary fixing film 13 in such a manner as to cover a plurality of solder precoats (11) formed on a plurality of lands (10b) on a substrate and an antioxidation film (12) formed in such a manner as to cover the solder precoats; a step (ii) of disposing a plurality of electronic components (30) on the plurality of solder precoats (11) via the antioxidation film (12) and the temporary fixing film (13); and a step (iii) of soldering the plurality of electronic components (30) to the plurality of lands (10b) by melting the plurality of solder precoats (11). The antioxidation film (12) contains a first thermoplastic resin. The temporary fixing film (13) contains an activating agent and a second thermoplastic resin. The softening point of the second thermoplastic resin is equal to or lower than the softening point of the first thermoplastic resin.

公开(公告)号：US12027433B2

公开(公告)日：2024-07-02

申请号：US17885401

申请日：2022-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yang-Che Chen ,  Chen-Hua Lin ,  Huang-Wen Tseng ,  Victor Chiang Liang ,  Chwen-Ming Liu

IPC分类号： H01L21/52 ,  H01L23/00 ,  H01L23/04 ,  H01L23/06 ,  H01L23/14 ,  H01L23/498 ,  H01L21/60

CPC分类号： H01L23/04 ,  H01L21/52 ,  H01L23/06 ,  H01L23/14 ,  H01L23/49816 ,  H01L24/14 ,  H01L2021/60022

摘要： A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

公开(公告)号：US11990418B2

公开(公告)日：2024-05-21

申请号：US17459266

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua Wang ,  Po-Chen Lai ,  Ping-Tai Chen ,  Che-Chia Yang ,  Yu-Sheng Lin ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/60 ,  H01L21/76802 ,  H01L24/80 ,  H01L25/0655

摘要： A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.

公开(公告)号：US20240145459A1

公开(公告)日：2024-05-02

申请号：US18407222

申请日：2024-01-08

申请人： Silicon Genesis Corporation

发明人： Michael I. CURRENT ,  Theodore E. FONG

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L21/60 ,  H01L21/76802 ,  H01L21/78 ,  H01L24/95 ,  H01L25/0657

摘要： A three-dimensional integrated circuit (3DIC) includes an interconnect network layer having a first plurality of electrodes on a lower surface, a second plurality of electrodes on an upper surface, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes, a lower device structure with upper electrodes respectively bonded to electrodes of the first plurality of electrodes on the lower surface of the interconnect network layer, and an upper device structure with lower electrodes respectively bonded to electrodes of the second plurality of electrodes on the upper surface of the interconnect network layer. The interconnect network layer can link several diverse dies in lateral and vertical directions.

公开(公告)号：US11973062B2

公开(公告)日：2024-04-30

申请号：US18169735

申请日：2023-02-15

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49827 ,  H01L2021/60037

摘要： A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.