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    Page buffer enhancements
    3.
    发明授权
    Page buffer enhancements 有权

    公开(公告)号：US12112070B2

    公开(公告)日：2024-10-08

    申请号：US18204858

    申请日：2023-06-01

    申请人： Kioxia Corporation

    发明人： Neil Buxton ,  Avadhani Shridhar ,  Steven Wells ,  Nicole Ross

    IPC分类号： G06F3/06 ,  G11C16/04 ,  G11C11/56

    CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/56

    摘要： A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

    Non-volatile memory device and a method for operating the same
    4.
    发明授权
    Non-volatile memory device and a method for operating the same 有权

    公开(公告)号：US12112056B2

    公开(公告)日：2024-10-08

    申请号：US18202692

    申请日：2023-05-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hyun Joo

    IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/14 ,  G11C16/16

    CPC分类号： G06F3/0652 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/16 ,  G11C2211/5642

    摘要： In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.

    REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS
    6.
    发明公开
    REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS 审中-公开

    公开(公告)号：US20240321350A1

    公开(公告)日：2024-09-26

    申请号：US18734724

    申请日：2024-06-05

    申请人： Micron Technology, Inc.

    发明人： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

    IPC分类号： G11C13/00 ,  G11C11/56

    CPC分类号： G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C11/5678

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.