公开(公告)号：US12094527B2

公开(公告)日：2024-09-17

申请号：US17709794

申请日：2022-03-31

申请人： International Business Machines Corporation

发明人： Rajiv Joshi ,  Sudipto Chakraborty

IPC分类号： G11C11/412 ,  G06N3/065 ,  G11C11/418 ,  G11C11/419 ,  H03M1/66

CPC分类号： G11C11/418 ,  G06N3/065 ,  G11C11/412 ,  G11C11/419 ,  H03M1/66

摘要： An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.

公开(公告)号：US20240282367A1

公开(公告)日：2024-08-22

申请号：US18639330

申请日：2024-04-18

申请人： Samsung Electronics Co., Ltd.

发明人： Taemin Choi ,  Taehyun Kim ,  Seongook Jung

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

公开(公告)号：US20240249769A1

公开(公告)日：2024-07-25

申请号：US18626860

申请日：2024-04-04

申请人： NUMEM Inc.

发明人： Bindiganavale S. Nataraj

IPC分类号： G11C11/419 ,  G06N3/04 ,  G06N3/063 ,  G11C11/418 ,  H03K19/20 ,  H03K19/21

CPC分类号： G11C11/419 ,  G06N3/04 ,  G06N3/063 ,  G11C11/418 ,  H03K19/20 ,  H03K19/21

摘要： A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes selection logic coupled to the plurality of logic gates. The selection logic includes a two dimensional (2D) associative array to generate select lines associated with a first pair of rows of memory cells. The select lines are configured to provide enable signals to the plurality of logic gates to control compute operations of the array.

公开(公告)号：US12046275B2

公开(公告)日：2024-07-23

申请号：US17558176

申请日：2021-12-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ruchi Shankar ,  Shobhit Singhal ,  Sverre Brubæk ,  Praveen Kumar Narayanan

IPC分类号： G06F9/445 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/412 ,  G11C11/419 ,  G11C11/418

摘要： A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.

公开(公告)号：US12041761B2

公开(公告)日：2024-07-16

申请号：US18182489

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC分类号： H10B10/00 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

CPC分类号： H10B10/12 ,  G11C11/418 ,  H01L23/528 ,  H01L27/0207 ,  H10B10/18

摘要： A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US20240161820A1

公开(公告)日：2024-05-16

申请号：US18503479

申请日：2023-11-07

申请人： Robert Bosch GmbH

发明人： Taha Soliman ,  Tobias Kirchner

IPC分类号： G11C11/412 ,  G11C5/06 ,  G11C11/418

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C11/418

摘要： A method for operating a memory device comprising at least one memory unit. The at least one memory unit includes a bistable multivibrator and two access transistors for the controllable connection of the bistable multivibrator to two secondary control lines associated with the at least one memory unit. The connection of the bistable multivibrator to the two secondary control lines can be controlled using a first primary control line. The method includes: applying a control signal to a control terminal of at least one of the two access transistors in such a way that a load path of the at least one access transistor is at least partially electrically conductive, with respect to a high-resistance state of the load path of the at least one access transistor; determining a first variable which characterizes at least one current flowing through the load path of the at least one access transistor.

公开(公告)号：US20240135988A1

公开(公告)日：2024-04-25

申请号：US17971226

申请日：2022-10-20

申请人： Arm Limited

发明人： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419

摘要： Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US11948627B2

公开(公告)日：2024-04-02

申请号：US17818386

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/013

CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/0136

摘要： A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US11922998B2

公开(公告)日：2024-03-05

申请号：US17752319

申请日：2022-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Atul Katoch ,  Sahil Preet Singh

IPC分类号： G11C11/418 ,  G11C11/412

CPC分类号： G11C11/418 ,  G11C11/412

摘要： A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

公开(公告)号：US20240069096A1

公开(公告)日：2024-02-29

申请号：US18228048

申请日：2023-07-31

申请人： STMicroelectronics International N.V.

发明人： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC分类号： G01R31/317 ,  G11C11/418 ,  G11C11/419

CPC分类号： G01R31/31724 ,  G11C11/418 ,  G11C11/419

摘要： An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.