Circuitry for memory address collision prevention

    公开(公告)号:US12066926B2

    公开(公告)日:2024-08-20

    申请号:US17861084

    申请日:2022-07-08

    申请人: Arm Limited

    IPC分类号: G06F12/02

    CPC分类号: G06F12/023 G06F2212/1008

    摘要: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

    Cell architecture
    3.
    发明授权

    公开(公告)号:US11557583B2

    公开(公告)日:2023-01-17

    申请号:US17017551

    申请日:2020-09-10

    申请人: Arm Limited

    摘要: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

    Memory Compiler Techniques
    4.
    发明申请

    公开(公告)号:US20210389934A1

    公开(公告)日:2021-12-16

    申请号:US16899502

    申请日:2020-06-11

    申请人: Arm Limited

    摘要: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.

    Segmented memory instances
    6.
    发明授权

    公开(公告)号:US10521532B1

    公开(公告)日:2019-12-31

    申请号:US16125158

    申请日:2018-09-07

    申请人: Arm Limited

    IPC分类号: G06F17/50 G06F17/40

    摘要: Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.

    Circuitry for Memory Address Collision Prevention

    公开(公告)号:US20240012748A1

    公开(公告)日:2024-01-11

    申请号:US17861084

    申请日:2022-07-08

    申请人: Arm Limited

    IPC分类号: G06F12/02

    CPC分类号: G06F12/023 G06F2212/1008

    摘要: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.