公开(公告)号：US11557583B2

公开(公告)日：2023-01-17

申请号：US17017551

申请日：2020-09-10

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/3953 ,  G06F30/392 ,  H01L23/48

Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

公开(公告)号：US20240153551A1

公开(公告)日：2024-05-09

申请号：US17980335

申请日：2022-11-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Vivek Asthana ,  Sony ,  Ettore Amirante ,  Yew Keong Chong

IPC: G11C11/418

CPC classification number: G11C11/418

Abstract: Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.

公开(公告)号：US11380384B2

公开(公告)日：2022-07-05

申请号：US17006689

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/413

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US20220122654A1

公开(公告)日：2022-04-21

申请号：US17076305

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony

IPC: G11C11/417 ,  H01L27/11

Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.

公开(公告)号：US12218664B2

公开(公告)日：2025-02-04

申请号：US17076549

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Rajiv Kumar Sisodia

IPC: G11C11/00 ,  G11C11/417 ,  H03K19/00 ,  G06F113/04

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

公开(公告)号：US20220123751A1

公开(公告)日：2022-04-21

申请号：US17076549

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Rajiv Kumar Sisodia

IPC: H03K19/00 ,  G11C11/417

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

公开(公告)号：US20220122656A1

公开(公告)日：2022-04-21

申请号：US17076540

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G11C11/418

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

公开(公告)号：US20220077857A1

公开(公告)日：2022-03-10

申请号：US17013199

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H03K19/17736 ,  H03K19/1776

Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.

公开(公告)号：US12164855B2

公开(公告)日：2024-12-10

申请号：US17209903

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Andy Wangkun Chen

IPC: G06F30/3953

Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

公开(公告)号：US11837543B2

公开(公告)日：2023-12-05

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L27/0688

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.