-
公开(公告)号：US20240363187A1
公开(公告)日：2024-10-31
申请号：US18635569
申请日：2024-04-15
发明人： Praveen Kumar VERMA , Christophe LECOCQ , Yagnesh Dineshbhai VADERIYA , Anuj DHILLON , Cedric ESCALLIER , Harsh RAWAT , Kedar Janardan DHORI
CPC分类号： G11C29/46 , G11C29/022 , G11C29/32 , G11C2029/3202
摘要： A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.
-
2.发明公开公开(公告)号：US20230410862A1
公开(公告)日：2023-12-21
申请号：US18136491
申请日：2023-04-19
摘要： An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.
-
公开(公告)号：US20230350483A1
公开(公告)日：2023-11-02
申请号：US18338950
申请日：2023-06-21
发明人： Nitin CHAWLA , Anuj GROVER , Giuseppe DESOLI , Kedar Janardan DHORI , Thomas BOESCH , Promod KUMAR
IPC分类号： G05F3/24 , G11C11/413 , G06F1/3234 , G06F1/3287 , G06F15/78
CPC分类号： G06F1/3275 , G05F3/24 , G06F1/3287 , G06F15/7821 , G11C11/413
摘要： Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
-
4.发明公开公开(公告)号：US20240143239A1
公开(公告)日：2024-05-02
申请号：US18379373
申请日：2023-10-12
发明人： Bhupender SINGH , Hitesh CHAWLA , Tanuj KUMAR , Harsh RAWAT , Kedar Janardan DHORI , Promod KUMAR , Manuj AYODHYAWASI , Nitin CHAWLA
IPC分类号： G06F3/06
CPC分类号： G06F3/0673 , G06F3/061 , G06F3/0655
摘要： A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.
-
公开(公告)号：US20230410892A1
公开(公告)日：2023-12-21
申请号：US18137261
申请日：2023-04-20
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4096 , G11C11/4094 , G11C11/4074 , G11C11/4085
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
-
6.发明公开公开(公告)号：US20230386564A1
公开(公告)日：2023-11-30
申请号：US18137159
申请日：2023-04-20
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4094
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.
-
公开(公告)号：US20230012567A1
公开(公告)日：2023-01-19
申请号：US17844955
申请日：2022-06-21
IPC分类号： G11C11/418 , G11C11/412 , G11C11/419
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.
-
公开(公告)号：US20240112728A1
公开(公告)日：2024-04-04
申请号：US18244782
申请日：2023-09-11
发明人： Harsh RAWAT , Kedar Janardan DHORI , Dipti ARYA , Promod KUMAR , Nitin CHAWLA , Manuj AYODHYAWASI
IPC分类号： G11C11/418 , G11C11/412 , G11C11/419
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , H03M1/12
摘要： A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.
-
9.发明公开公开(公告)号：US20240071439A1
公开(公告)日：2024-02-29
申请号：US18233522
申请日：2023-08-14
CPC分类号： G11C7/109 , G11C7/1087 , G11C7/1096 , G11C7/12
摘要： The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.
-
公开(公告)号：US20230386566A1
公开(公告)日：2023-11-30
申请号：US18137191
申请日：2023-04-20
IPC分类号： G11C11/419 , G11C11/418 , G11C11/412 , H03M1/46
CPC分类号： G11C11/419 , G11C11/418 , G11C11/412 , H03M1/46
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.018 秒)
