公开(公告)号：US20240363175A1

公开(公告)日：2024-10-31

申请号：US18768926

申请日：2024-07-10

申请人： KIOXIA CORPORATION

发明人： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA

IPC分类号： G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

CPC分类号： G11C16/34 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/0483

摘要： According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

公开(公告)号：US20240362176A1

公开(公告)日：2024-10-31

申请号：US18764940

申请日：2024-07-05

申请人： STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

发明人： Fred Rennig ,  Ludek Beran

IPC分类号： G06F13/362 ,  G05B19/042 ,  G06F9/54 ,  G06F11/07 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42 ,  H03M13/09 ,  H04L12/40 ,  H04L12/403

CPC分类号： G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1004 ,  G06F13/4068 ,  G06F13/4282 ,  H04L12/40006 ,  H04L12/40013 ,  H04L12/40078 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09 ,  H04L2012/40215

摘要： A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20240361922A1

公开(公告)日：2024-10-31

申请号：US18767906

申请日：2024-07-09

申请人： Kioxia Corporation

发明人： Daisuke HASHIMOTO

IPC分类号： G06F3/06 ,  G06F1/26 ,  G06F11/10 ,  G06F12/02 ,  G11C5/14 ,  G11C29/52

CPC分类号： G06F3/0619 ,  G06F3/0614 ,  G06F3/0625 ,  G06F12/0246 ,  G06F1/266 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0688 ,  G06F11/1068 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/263 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C5/144 ,  G11C5/147 ,  G11C5/148 ,  G11C29/52 ,  Y02D10/00

摘要： A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.

公开(公告)号：US12132501B2

公开(公告)日：2024-10-29

申请号：US17895227

申请日：2022-08-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wonjae Shin ,  Sung-Joon Kim ,  Heedong Kim ,  Minsu Bae ,  Ilwoong Seo ,  Mijin Lee ,  Seung Ju Lee ,  Hyan Suk Lee ,  Insu Choi ,  Kideok Han

IPC分类号： H03M13/19 ,  G06F11/10 ,  G11C5/04 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/00

CPC分类号： H03M13/19 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/611 ,  G11C5/04

摘要： A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US12131024B2

公开(公告)日：2024-10-29

申请号：US18204854

申请日：2023-06-01

申请人： Kioxia Corporation

发明人： Shinichi Kanno ,  Hiroshi Nishimura ,  Hideki Yoshida ,  Hiroshi Murayama

IPC分类号： G06F3/06 ,  G06F1/3234 ,  G06F11/10 ,  G06F12/02 ,  G11C16/04 ,  G11C16/24 ,  G11C29/52 ,  H03M13/29

CPC分类号： G06F3/0604 ,  G06F1/3275 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/2906 ,  G06F12/0246 ,  G06F2212/214 ,  G11C16/0483 ,  G11C16/24 ,  Y02D10/00

摘要： A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

公开(公告)号：US12130813B2

公开(公告)日：2024-10-29

申请号：US18534912

申请日：2023-12-11

申请人： Ocient Holdings LLC

发明人： George Kondiles ,  Jason Arnold

IPC分类号： G06F16/00 ,  G06F3/06 ,  G06F7/24 ,  G06F9/4401 ,  G06F9/50 ,  G06F11/10 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/17 ,  G06F16/22 ,  G06F16/23 ,  G06F16/242 ,  G06F16/2453 ,  G06F16/2455 ,  G06F16/2457 ,  G06F16/2458 ,  G06F16/27 ,  G06F16/901 ,  H03M7/30 ,  H04L67/10

CPC分类号： G06F16/24542 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/068 ,  G06F7/24 ,  G06F9/4406 ,  G06F9/5016 ,  G06F9/5027 ,  G06F9/5061 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/1076 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/1727 ,  G06F16/22 ,  G06F16/2246 ,  G06F16/2282 ,  G06F16/2365 ,  G06F16/244 ,  G06F16/2445 ,  G06F16/2453 ,  G06F16/24553 ,  G06F16/24573 ,  G06F16/2458 ,  G06F16/278 ,  G06F16/901 ,  G06F16/9017 ,  H03M7/30 ,  H04L67/10 ,  G06F3/067 ,  G06F16/24547 ,  G06F2211/1011 ,  G06F2212/608

摘要： A node of a computing system includes a main memory and a plurality of processing core resources. The main memory includes a computing device section and a database section. The computing device section includes a computing device operating system area and a computing device general area. The database section includes a database section that includes a database operating system area, a disk area, a network area, and a database general area. The database operating system area allocates at least one portion of the main memory for database operations that is locked from access by the computing device operating system area.

公开(公告)号：US12130717B2

公开(公告)日：2024-10-29

申请号：US18514317

申请日：2023-11-20

申请人： PURE STORAGE, INC.

发明人： John Hayes ,  John Colgrove ,  Robert Lee ,  Joshua Robinson ,  Rusty Sears

IPC分类号： G06F11/20 ,  G06F11/10

CPC分类号： G06F11/2056 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096

摘要： A method for proactively rebuilding user data in a plurality of storage nodes of a storage cluster in a single chassis is provided. The method includes distributing user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can read the user data, using erasure coding, despite loss of two of the plurality of storage nodes. The method includes determining to rebuild the user data for one of the plurality of storage nodes in the absences of an error condition. The method includes rebuilding the user data for the one of the plurality of storage nodes. A plurality of storage nodes within a single chassis that can proactively rebuild the user data stored within the storage nodes is also provided.

公开(公告)号：US12130703B2

公开(公告)日：2024-10-29

申请号：US18230403

申请日：2023-08-04

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

IPC分类号： H03M13/27 ,  G06F11/10 ,  H03M13/25 ,  H04L1/00 ,  H04L27/34

CPC分类号： G06F11/1076 ,  G06F11/1048

摘要： A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20240354260A1

公开(公告)日：2024-10-24

申请号：US18762987

申请日：2024-07-03

申请人： Texas Instruments Incorporated

发明人： Timothy David Anderson ,  Mujibur Rahman

IPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

公开(公告)号：US20240354190A1

公开(公告)日：2024-10-24

申请号：US18759122

申请日：2024-06-28

申请人： Intel Corporation

发明人： Junjing SHI ,  Wei YANG ,  Amir Ali RADJAI ,  Hongjiu LU

IPC分类号： G06F11/10

CPC分类号： G06F11/1016 ,  G06F11/1004

摘要： Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.