公开(公告)号：US09468091B2

公开(公告)日：2016-10-11

申请号：US13960897

申请日：2013-08-07

Applicant: Chien-Cheng Wei ,  Wu-Hui Cheng

Inventor： Chien-Cheng Wei ,  Wu-Hui Cheng

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/00 ,  H05K1/03 ,  H05K3/10 ,  H05K3/14 ,  H05K3/16 ,  H05K3/38

CPC classification number: H05K1/0271 ,  H05K1/0265 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/108 ,  H05K3/146 ,  H05K3/16 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/09845 ,  H05K2203/058 ,  H05K2203/1476 ,  H05K2203/1572

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract translation: 应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。 第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化 绝缘基板和第一和第二导电层。

公开(公告)号：US20150208501A1

公开(公告)日：2015-07-23

申请号：US14417751

申请日：2013-05-17

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro Hayashi ,  Makoto Nagai ,  Seiji Mori ,  Tomohiro Nishida ,  Makoto Wakazono ,  Tatsuya Ito

IPC: H05K1/11 ,  G03F7/30 ,  G03F7/20 ,  H05K1/02

CPC classification number: H05K1/111 ,  G03F7/038 ,  G03F7/20 ,  G03F7/2024 ,  G03F7/30 ,  H01L23/49822 ,  H01L2224/16237 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/058 ,  H05K2203/0594 ,  H05K2203/1476

Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

Abstract translation: 提供与半导体芯片的连接可靠性优异的布线板。 在有机布线板10的基板主表面11侧形成有树脂绝缘层21,22和导体层24层叠的第一堆积层31.第一堆积层31中的最外层的导体层24包括 多个用于倒装芯片安装半导体芯片的连接端子部分41。 多个连接端子部分41通过阻焊层25的开口部分43露出。每个连接端子部分41包括用于半导体芯片的连接区域51和从连接区域51延伸的布线区域52 平面方向。 阻焊层25在开口部43内具有覆盖连接端子部41的侧面的侧面覆盖部55和与侧面覆盖部55一体形成的突出壁部56， 被设置为突出以与连接区域51相交。

公开(公告)号：US07122905B2

公开(公告)日：2006-10-17

申请号：US10621194

申请日：2003-07-15

Applicant: Ford B. Grigg

Inventor： Ford B. Grigg

IPC: H01L23/48

CPC classification number: H05K3/3436 ,  H01L2224/4824 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/3489 ,  H05K2201/09472 ,  H05K2201/0989 ,  H05K2201/10977 ,  H05K2203/0195 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0537 ,  H05K2203/058 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.

Abstract translation: 封装的微电子器件，制造封装的微电子器件的方法以及将封装的微电子器件安装到印刷电路板的方法。 一个实施例可以包括管芯，插入器衬底，焊球和电介质化合物。 芯片可以具有集成电路和耦合到集成电路的至少一个接合焊盘。 插入器基板耦合到管芯并且可以具有至少一个电焊接到管芯上的焊盘的球焊盘。 插入器基板还可以具有与球垫相邻的迹线，以及在球垫上具有开口的焊接掩模。 焊球可以接触开口中的球垫。 电介质化合物可以使球垫和焊球与开口中的相邻轨迹线的暴露部分绝缘。

公开(公告)号：US07005241B2

公开(公告)日：2006-02-28

申请号：US10822825

申请日：2004-04-13

Applicant: Katsuya Fukase ,  Toyoaki Sakai

Inventor： Katsuya Fukase ,  Toyoaki Sakai

IPC: G03F7/00

CPC classification number: G03F7/0035 ,  H01L21/4828 ,  H01L21/4846 ,  H05K3/062 ,  H05K3/064 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1476

Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.

Abstract translation: 制造电路板的方法包括以下步骤：通过位于金属层的上表面上的第一掩模半蚀刻在绝缘基板上形成的金属层; 从第一掩模的上侧在半蚀刻金属层上施加正的液体抗蚀剂; 以平行的光从第一掩模的上侧露出正的液体抗蚀剂，并以这样的方式显影出正的液体抗蚀剂，使得位于第一掩蔽下的正极抗蚀剂的一部分被保护为未曝光和未显影; 通过由第一掩模和受保护的正性液体抗蚀剂构成的第二掩模再次蚀刻金属层，以在绝缘基板上形成导电图案; 以及从金属层去除第一掩蔽和第二掩蔽。

公开(公告)号：US09699916B2

公开(公告)日：2017-07-04

申请号：US14707295

申请日：2015-05-08

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro Hayashi

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/28 ,  H05K1/02 ,  H05K3/46 ,  H05K3/18 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40

CPC classification number: H05K3/28 ,  H05K1/0284 ,  H05K3/188 ,  H05K3/243 ,  H05K3/244 ,  H05K3/282 ,  H05K3/381 ,  H05K3/383 ,  H05K3/4007 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09409 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/10204 ,  H05K2203/0307 ,  H05K2203/0574 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/0766 ,  Y10T29/49156

Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.

公开(公告)号：US20150327371A1

公开(公告)日：2015-11-12

申请号：US14684831

申请日：2015-04-13

Applicant: MICROCOSM TECHNOLOGY CO., LTD.

Inventor： Tang-Chieh HUANG ,  Chau-Chin CHUANG

IPC: H05K3/00 ,  H05K3/46

CPC classification number: H05K3/4673 ,  H05K1/0393 ,  H05K3/0035 ,  H05K3/0091 ,  H05K3/46 ,  H05K2201/0154 ,  H05K2203/0571 ,  H05K2203/058

Abstract: A method of making a multilayer circuit board includes: forming and exposing a first polyimide photoresist layer; forming holes in the first polyimide photoresist layer; forming a second metal layer on the first polyimide photoresist layer; forming a first photoresist mask layer on the second metal layer; patterning the first photoresist mask layer and the second metal layer; forming a second polyimide photoresist layer on the patterned second metal layer; exposing the second polyimide photoresist layer; forming a hole in the second polyimide photoresist layer; forming a third metal layer on the second polyimide photoresist layer; and forming and patterning a second photoresist mask layer on the third metal layer.

Abstract translation: 制造多层电路板的方法包括：形成和曝光第一聚酰亚胺光致抗蚀剂层; 在第一聚酰亚胺光致抗蚀剂层中形成孔; 在所述第一聚酰亚胺光致抗蚀剂层上形成第二金属层; 在所述第二金属层上形成第一光致抗蚀剂掩模层; 图案化第一光致抗蚀剂掩模层和第二金属层; 在所述图案化的第二金属层上形成第二聚酰亚胺光致抗蚀剂层; 暴露第二聚酰亚胺光刻胶层; 在第二聚酰亚胺光致抗蚀剂层中形成孔; 在所述第二聚酰亚胺光刻胶层上形成第三金属层; 以及在所述第三金属层上形成和图案化第二光致抗蚀剂掩模层。

公开(公告)号：US20150060396A1

公开(公告)日：2015-03-05

申请号：US14456944

申请日：2014-08-11

Applicant: Sony Corporation

Inventor： Masahiro Kaida ,  Yuu Kawaguchi

IPC: C23F1/02 ,  G02B5/30 ,  H01B13/00 ,  C23F1/12

CPC classification number: G02B5/3025 ,  C23F4/00 ,  G02B5/3058 ,  H05K3/061 ,  H05K2203/058

Abstract: An etching process includes: forming a metal film on a substrate having a pattern formation region; forming a mask having a predetermined pattern on the metal film in the pattern formation region, and forming a resist film in part or all of a periphery of the pattern formation region; and dry-etching the metal film in the pattern formation region.

Abstract translation: 蚀刻工艺包括：在具有图案形成区域的基板上形成金属膜; 在图案形成区域中的金属膜上形成具有预定图案的掩模，并且在图案形成区域的周边部分或全部形成抗蚀剂膜; 并且在图案形成区域中干蚀刻金属膜。

公开(公告)号：US20130118792A1

公开(公告)日：2013-05-16

申请号：US13672063

申请日：2012-11-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Byung Seung MIN

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K1/02 ,  H05K3/10 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/054 ,  H05K2203/058 ,  H05K2203/0723

Abstract: Disclosed herein is a method for manufacturing a printed circuit board, including: applying a solder resist to an insulating material; forming a cavity in the insulating material and the solder resist; forming a seed layer on a surface of the insulating material including the inside of the cavity; forming circuit patterns by plating the inside of the cavity; removing the seed layer formed on the surface of the solder resist; reapplying the solder resist on the solder resist from which the seed layer is removed; and opening a bump forming region of the reapplied solder resist, whereby micro circuits can be easily implemented.

Abstract translation: 本发明公开了一种印刷电路板的制造方法，其特征在于，包括：向绝缘材料施加阻焊剂; 在绝缘材料和阻焊剂中形成空腔; 在包括所述空腔内部的所述绝缘材料的表面上形成种子层; 通过电镀内腔形成电路图案; 去除形成在阻焊剂表面上的种子层; 将阻焊剂重新施加到去除种子层的阻焊层上; 并且打开重新施加的阻焊剂的凸块形成区域，从而可以容易地实现微电路。

公开(公告)号：US20110024173A1

公开(公告)日：2011-02-03

申请号：US12585996

申请日：2009-09-30

Applicant: Jin-Chang Wu ,  Wen-bing Wang ,  Xun Wang

Inventor： Jin-Chang Wu ,  Wen-bing Wang ,  Xun Wang

IPC: H05K1/16 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/3452 ,  H05K3/3436 ,  H05K2201/10734 ,  H05K2203/058 ,  H05K2203/0597 ,  Y10T29/49149

Abstract: A BGA (ball grid array) printed circuit board is disclosed, which includes a substrate having a dielectric layer, a BGA pad and a solder mask formed on the dielectric layer, and an adhesive glue filled in a gap between the BGA pad and the solder mask. A BGA printed circuit board package structure and a method for fabricating the BGA printed circuit board are also disclosed.

Abstract translation: 公开了一种BGA（球栅阵列）印刷电路板，其包括具有介电层，BGA焊盘和形成在电介质层上的焊接掩模的基板，以及填充在BGA焊盘和焊料之间的间隙中的粘合胶 面具。 还公开了一种BGA印刷电路板封装结构和用于制造BGA印刷电路板的方法。

公开(公告)号：US20080202804A1

公开(公告)日：2008-08-28

申请号：US12033318

申请日：2008-02-19

Applicant: YASUHIRO FAKUTOMI ,  Yuuji Minota ,  Motonobu Koike

Inventor： YASUHIRO FAKUTOMI ,  Yuuji Minota ,  Motonobu Koike

IPC: H05K1/00 ,  B23K1/20

CPC classification number: H05K3/363 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10636 ,  H05K2201/10727 ,  H05K2201/2036 ,  H05K2203/0568 ,  H05K2203/058 ,  H05K2203/0588 ,  H05K2203/1476 ,  Y02P70/611

Abstract: There is provided a printed circuit board in which space between pads used for surface mounting can be narrowed and an FPC can be mounted along with electronic components by the reflow method even when the FPC is mounted and a method of producing the same. A printed circuit board is configured such that a solder resist 3 is formed on the surface of the printed circuit board so as to expose pads 2, a solder resist 4 is formed between the adjacent pads, and solder paste which is as high as or higher than the solder resist 4 is provided by printing on the pad 2 separated from other pads 2 by the solder resists 3 and 4.

Abstract translation: 提供了一种印刷电路板，其中用于表面安装的焊盘之间的空间可以变窄，并且即使在安装FPC时也可以通过回流法与电子部件一起安装FPC以及其制造方法。 印刷电路板被构造成使得在印刷电路板的表面上形成阻焊剂3，以便露出焊盘2，在相邻的焊盘之间形成阻焊剂4，并且焊膏高达或高于 比通过由阻焊剂3和4与其它焊盘2分离的焊盘2上印刷提供阻焊剂4。