公开(公告)号：US4254345A

公开(公告)日：1981-03-03

申请号：US040828

申请日：1979-05-21

申请人： Manfred F. Ullrich

发明人： Manfred F. Ullrich

IPC分类号： G11C19/18 ,  H01L27/105 ,  G11C19/28 ,  H01L29/78

CPC分类号： G11C19/186 ,  H01L27/1055

摘要： To reduce the D.C drift of bucket-brigade devices having common output circuits (emitter follower), an output circuit is provided having an additional transistor and an additional capacitor. The terminal on the gate side of the capacitor associated with the last delaying transistor is not connected to the gate terminal but to the source terminal of the output transistor, the gate terminal of the terminating transistor is applied via the additional capacitor to that particular clock signal to which the penultimate delaying transistor is applied, and the drain terminal of the terminating transistor, via an enhancement-type transistor of the same conductivity, connected as a diode by directly connecting both the drain and the gate terminals, is connected to the gate terminal thereof.

摘要翻译： 为了减少具有公共输出电路（射极跟随器）的斗式装置的D.C漂移，提供具有附加晶体管和附加电容器的输出电路。 与最后延迟晶体管相关的电容器的栅极侧的端子不连接到栅极端子，而是连接到输出晶体管的源极端子，端接晶体管的栅极端子经由附加电容器施加到该特定的时钟信号 通过直接连接两个漏极和栅极端子连接作为二极管的相同导电性的增强型晶体管，终端晶体管的漏极端子连接到栅极端子 其中。

公开(公告)号：US4142199A

公开(公告)日：1979-02-27

申请号：US809876

申请日：1977-06-24

申请人： Victor M. Simi ,  Donald A. Soderman

发明人： Victor M. Simi ,  Donald A. Soderman

IPC分类号： H01L21/339 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/07 ,  H01L27/105 ,  H01L29/76 ,  H01L29/762 ,  H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  G11C19/28

CPC分类号： H01L21/823406 ,  H01L21/2652 ,  H01L21/266 ,  H01L27/0733 ,  H01L27/1055

摘要： The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A thin n-type region is implanted in a portion of the p-type channel region of an FET device adjacent to the drain diffusion. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

摘要翻译： 本发明是用于制造桶式装置的结构和工艺，其包括MOS电容器与MOSFET器件的合并以形成电荷转移电池。 在与漏极扩散相邻的FET器件的p型沟道区域的一部分中注入薄的n型区域。 这种结构增加了电池的电荷转移效率，并降低了其阈值电压对源极 -​​ 漏极电压的灵敏度。 用于器件的栅极在漏极上具有实质重叠，并且源极上的最小重叠，并且通过在栅极区域上保持均匀薄的氧化物层来最大化每单位面积的栅极至漏极电容。

公开(公告)号：US3986176A

公开(公告)日：1976-10-12

申请号：US585410

申请日：1975-06-09

申请人： Paul Kessler Weimer

发明人： Paul Kessler Weimer

IPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/406 ,  G11C14/00 ,  G11C19/28 ,  H01L27/105 ,  G11C7/00

CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/406 ,  G11C14/00 ,  G11C19/287 ,  H01L27/1055 ,  H01L27/1057

摘要： Charge transfer memories such as those of the bucket-brigade or of the charge-coupled device (CCD) type include, at each location, a store which is separate from the normal means for charge storage. Charge is transferred from the normal means of storage to the separate store at each location during a first period of time and may be sensed during later intervals of time to provide multiple "copies" of the stored information. In one form of such a memory especially suitable for the storage of digital data, each separate store includes an internal loop for refreshing the charge. In other forms of such memories, means are provided for reducing the effects of variation in threshold voltage from location-to-location of the transistors associated with the separate stores. These are especially suitable for analog storage.

摘要翻译： 电荷转移存储器，例如桶式电池或电荷耦合器件（CCD）类型的电荷转移存储器在每个位置处包括与用于电荷存储的正常装置分离的存储器。 在第一时间段期间，电费从正常存储装置传送到每个位置处的单独存储器，并且可以在稍后的时间间隔期间感测以提供所存储的信息的多个“复制”。 在特别适合于存储数字数据的这种存储器的一种形式中，每个单独的存储器包括用于刷新电荷的内部循环。 在这种存储器的其他形式中，提供了用于减少与单独存储器相关联的晶体管的位置到位置的阈值电压变化的影响的装置。 这些特别适用于模拟存储。

公开(公告)号：US3867645A

公开(公告)日：1975-02-18

申请号：US39355573

申请日：1973-08-31

申请人： RCA CORP

发明人： WEIMER PAUL KESSLER

IPC分类号： G11C27/04 ,  H01L27/105 ,  H03F1/26 ,  H03F3/00 ,  H03F3/16 ,  H03F3/70 ,  H03H11/26 ,  H03H15/02 ,  G11C11/24 ,  G11C11/40 ,  G11C19/00 ,  H01L19/00

CPC分类号： H03F3/005 ,  G11C27/04 ,  H01L27/1055 ,  H03F1/26 ,  H03F3/16 ,  H03H15/02

摘要： A charge transfer circuit for amplifying relatively low signal levels. The circuit includes a charge transfer register for propagating a charge signal along the register. Amplifying means are coupled along the register for sensing and amplifying the charge signal. The outputs of the amplifying means are then summed to produce an output signal having a high signal-to-noise ratio.

摘要翻译： 一种用于放大相对较低信号电平的电荷传输电路。 该电路包括用于沿寄存器传播电荷信号的电荷转移寄存器。 放大装置沿着寄存器耦合以感测和放大电荷信号。 然后将放大装置的输出相加以产生具有高信噪比的输出信号。

公开(公告)号：US3789240A

公开(公告)日：1974-01-29

申请号：US3789240D

申请日：1972-05-26

申请人： RCA CORP

发明人： WEIMER P

IPC分类号： H01L27/105 ,  H01L27/148 ,  H04N3/15 ,  H03K23/22

CPC分类号： H01L27/1055 ,  H01L27/14831 ,  H04N5/3742

摘要： A sensor array having photosensitive elements formed as an integral part of each stage of a shift register chain. Each stage has charge storage means. The photosensitive elements are coupled to the charge storage means for discharging them as a function of externally applied photo signals and, consequently, developing charge deficits in said charge storage means. The shift register, in response to a clocking signal, transfers the charge deficits from one stage to the next along the chain producing a serial output signal at an output terminal.

摘要翻译： 具有形成为移位寄存器链的每个级的组成部分的感光元件的传感器阵列。 每个阶段都有电荷存储装置。 感光元件耦合到电荷存储装置，用于根据外部施加的光信号放电它们，并因此在所述电荷存储装置中产生电荷缺陷。 移位寄存器响应于时钟信号，将电荷缺陷从链路的一个级传送到下一级，从而在输出端产生串行输出信号。

公开(公告)号：US3683193A

公开(公告)日：1972-08-08

申请号：US3683193D

申请日：1970-10-26

申请人： RCA CORP

发明人： WEIMER PAUL KESSLER

IPC分类号： H01L27/105 ,  H01L27/148 ,  H01J39/12 ,  H03K3/42 ,  H03K21/00

CPC分类号： H01L27/14831 ,  H01L27/1055 ,  H04N5/3742

摘要： A sensor array having photosensitive elements formed as an integral part of each stage of a shift register chain. Each stage has charge storage means. The photosensitive elements are coupled to the charge storage means for discharging them as a function of externally applied photo signals and, consequently, developing charge deficits in said charge storage means. The shift register, in response to a clocking signal, transfers the charge deficits from one stage to the next along the chain producing a serial output signal at an output terminal.

摘要翻译： 具有形成为移位寄存器链的每个级的组成部分的感光元件的传感器阵列。 每个阶段都有电荷存储装置。 感光元件耦合到电荷存储装置，用于根据外部施加的光信号放电它们，并因此在所述电荷存储装置中产生电荷缺陷。 移位寄存器响应于时钟信号，将电荷缺陷从链路的一个级传送到下一级，从而在输出端产生串行输出信号。

公开(公告)号：US3621283A

公开(公告)日：1971-11-16

申请号：US3621283D

申请日：1969-04-17

申请人： PHILIPS CORP

发明人： TEER KEES ,  SANGSTER FREDERIK LEONARD JOHA

IPC分类号： H01L27/105 ,  H01L27/148 ,  H04N5/374 ,  G06G7/12

CPC分类号： H01L27/1055 ,  H01L27/14831 ,  H04N5/3742

摘要： A device for converting energy patterns in the form of pressure, heat or magnetic images into an electrical signal as a function of time where the necessity for a scanning beam or a crossed bar readout system is eliminated by cascading elements which function as both storage and energy sensitive devices and by providing circuitry for shifting the charges of the energy sensitive storage elements in a single direction along the cascaded array.

公开(公告)号：US4157558A

公开(公告)日：1979-06-05

申请号：US901566

申请日：1978-05-01

申请人： Gene P. Weckler

发明人： Gene P. Weckler

IPC分类号： G06G7/19 ,  G11C11/24 ,  G11C11/34 ,  H01L21/70 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/105 ,  H03H15/02 ,  H01L29/78 ,  G11C19/28 ,  H01L29/04 ,  H03H7/28

CPC分类号： G11C11/34 ,  G06G7/1907 ,  G11C11/24 ,  H01L21/70 ,  H01L27/1055 ,  H03H15/02

摘要： An MOS bucket-brigade device (BBD) fabricated with two layers of polycrystalline silicon is disclosed. Each stage includes a pair of spaced-apart regions, one of which is formed in a well. A holding stage is employed which includes a lightly doped substrate region which reduces junction capacitance.

摘要翻译： 公开了一种用两层多晶硅制造的MOS桶式装置（BBD）。 每个阶段包括一对间隔开的区域，其中一个区域形成在井中。 采用保持级，其包括减少结电容的轻掺杂衬底区域。

公开(公告)号：US4100513A

公开(公告)日：1978-07-11

申请号：US710596

申请日：1976-08-02

申请人： Gene P. Weckler

发明人： Gene P. Weckler

IPC分类号： G06G7/19 ,  G11C11/24 ,  G11C11/34 ,  H01L21/70 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/105 ,  H03H15/02 ,  H03H7/10 ,  H03H7/28 ,  H03H7/30 ,  H03K5/159

CPC分类号： G11C11/34 ,  G06G7/1907 ,  G11C11/24 ,  H01L21/70 ,  H01L27/1055 ,  H03H15/02

摘要： A semiconductor filtering apparatus substantially fabricated as a metal-oxide-semiconductor (MOS) integrated circuit that permits discrete time correlation or convolution of an analog input signal with a binary or analog correlating signal. The apparatus may also be employed as a recursive filter. A plurality of novel bucket-brigade charge transfer means are employed to shift the input analog signal past non-destructive read-out taps. Electrically programmable floating gate devices are used to store either a binary or analog correlating signal. The sum or difference signal associated with each of the plurality of charge transfer means is weighted to produce the final filter output in one embodiment.

摘要翻译： 基本上制造为金属氧化物半导体（MOS）集成电路的半导体滤波装置，其允许模拟输入信号与二进制或模拟相关信号的离散时间相关或卷积。 该装置也可以用作递归滤波器。 采用多个新型的斗式旅行电荷转移装置将输入的模拟信号移动通过非破坏性读出抽头。 电可编程浮动栅极器件用于存储二进制或模拟相关信号。 在一个实施例中，与多个电荷转移装置中的每一个相关联的和或差分信号被加权以产生最终滤波器输出。

公开(公告)号：US4045810A

公开(公告)日：1977-08-30

申请号：US710021

申请日：1976-07-30

申请人： Walter J. Butler ,  Mark B. Barron ,  Bruno F. Kurz, deceased ,  by Elizabeth Kurz-Beerli, executrix, also known as Elisabeth H. Kurz

发明人： Walter J. Butler ,  Mark B. Barron ,  Bruno F. Kurz, deceased ,  by Elizabeth Kurz-Beerli, executrix, also known as Elisabeth H. Kurz

IPC分类号： H01L21/033 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/08 ,  H01L29/786 ,  H01L29/78 ,  G11C19/28

CPC分类号： H01L29/78606 ,  H01L21/033 ,  H01L21/823406 ,  H01L27/1055 ,  H01L29/0847

摘要： An MOS bucket brigade delay line having reduced parasitic capacitances include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.