公开(公告)号：US20170345515A1

公开(公告)日：2017-11-30

申请号：US15532343

申请日：2016-09-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG

IPC: G11C19/18 ,  G09G3/20 ,  G11C19/28

CPC classification number: G11C19/186 ,  G09G3/2096 ,  G09G2310/0286 ,  G11C19/287

Abstract: Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module having a first end connected to a second control signal end and a second end connected to the pull-up node, and being configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when output end is reset, the speed of resetting the output end can be increased.

公开(公告)号：US09424949B2

公开(公告)日：2016-08-23

申请号：US14481183

申请日：2014-09-09

Applicant: AU OPTRONICS CORP.

Inventor： Kai-Wei Hong ,  Pin-Yu Chan ,  Yung-Chih Chen ,  Li-Wei Liu

IPC: G11C19/00 ,  G11C19/28 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G2310/0286 ,  G11C19/186

Abstract: A shift register circuit includes a first transistor, a capacitor, a pull-up control circuit, a first pull-down circuit, a pull-down control circuit, a second pull-down circuit and a compensation circuit. The compensation circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The second transistor, the third transistor, the fourth transistor, and the fifth transistor are corporately used to output a compensation pulse; and the sixth transistor is used to output the compensation pulse to a gate terminal of the first transistor thereby compensating a control signal.

Abstract translation: 移位寄存器电路包括第一晶体管，电容器，上拉控制电路，第一下拉电路，下拉控制电路，第二下拉电路和补偿电路。 补偿电路还包括第二晶体管，第三晶体管，第四晶体管，第五晶体管和第六晶体管。 第二晶体管，第三晶体管，第四晶体管和第五晶体管共同地用于输出补偿脉冲; 并且第六晶体管用于将补偿脉冲输出到第一晶体管的栅极端子，从而补偿控制信号。

公开(公告)号：US4344001A

公开(公告)日：1982-08-10

申请号：US102839

申请日：1979-12-12

Applicant: Takao Tsuchiya ,  Mitsuo Soneda

Inventor： Takao Tsuchiya ,  Mitsuo Soneda

IPC: G11C19/18 ,  G11C19/28 ,  G11C27/04 ,  H03K5/00 ,  H03K17/56 ,  H03K17/60

CPC classification number: G11C19/285 ,  G11C19/186 ,  G11C27/04

Abstract: A clocking signal drive circuit supplies at least one clocking signal in a charge transfer device which has a plurality of successive capacitive storage elements for sequentially holding a charge level representing a time sampled input signal, with each of the capacitive storage elements having a clocking electrode for receiving one of a plurality of clocking signals so that the charge level representing the time sampled input signal is transferred from one to another of the capacitive storage means in succession in response to the clocking signals. The clocking signal drive circuit includes a clocking signal generator having an output at which the generator provides a clocking control signal, and a pair of complementary transistors each having first, second, and control electrodes, with the control electrode of the complementary transistors being connected together and to the output of the clocking signal generator and the first electrodes of the complementary transistors being connected together and to the clocking electrode of at least one of the capacitive storage elements. In one embodiment of the invention the clocking signal drive circuit functions as an output device for detecting the charge level on at least one of the capacitive storage elements of the charge transfer device, and further includes a detector for determining the amount of current which flows from the clocking signal drive circuit to the clocking electrode or electrodes to which it is connected.

Abstract translation: 时钟信号驱动电路在具有多个连续电容存储元件的电荷转移装置中提供至少一个时钟信号，用于顺序地保持表示时间采样输入信号的电荷电平，其中每个电容存储元件具有时钟电极 接收多个时钟信号中的一个，使得表示时间采样的输入信号的电荷电平响应于时钟信号被依次传送到电容存储装置的另一个。 时钟信号驱动电路包括具有发生器提供时钟控制信号的输出的时钟信号发生器，以及一对互补晶体管，每个互补晶体管具有第一，第二和控制电极，互补晶体管的控制电极连接在一起 以及时钟信号发生器的输出端和互补晶体管的第一电极连接在一起并连接到至少一个电容存储元件的时钟电极。 在本发明的一个实施例中，时钟信号驱动电路用作用于检测电荷转移装置的电容性存储元件中的至少一个上的电荷电平的输出装置，并且还包括用于确定从 时钟信号驱动电路连接到与其连接的时钟电极或电极。

公开(公告)号：US4156233A

公开(公告)日：1979-05-22

申请号：US852240

申请日：1977-11-17

Applicant: Charles M. Puckette ,  Walter J. Butler

Inventor： Charles M. Puckette ,  Walter J. Butler

IPC: H03M1/44 ,  G11C19/18 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H03M1/00 ,  H03K13/20

CPC classification number: G11C19/285 ,  G11C19/186 ,  H01L27/1055 ,  H03M1/804

Abstract: A monolithic analog to digital converter having leakage current compensating circuitry is disclosed. First and second charge storage capacitors are formed in a single semi-conductor substrate. An analog signal to be converted and a reference signal are simultaneously applied to the first and second capacitors, respectively. Thereafter, a charge transfer circuit supplies the first capacitor with a plurality of discrete charge packets. The polarity of the charge packets is chosen so as to increase or decrease the voltage across the first capacitor in the direction of the voltage across the second capacitor. When the voltage across the two capacitors become equal, a differential comparator generates an output signal indicating the end of a conversion operation. The parameters of the first and second capacitors are chosen such that the amount of charge added to or subtracted from the second capacitor due to a thermally induced leakage current in the substrate is substantially equal to the amount of charge added to or subtracted from the first capacitor as the result of the thermally induced leakage current.

Abstract translation: 公开了具有泄漏电流补偿电路的单片模/数转换器。 第一和第二电荷存储电容器形成在单个半导体衬底中。 要转换的模拟信号和参考信号分别同时施加到第一和第二电容器。 此后，电荷转移电路为第一电容器提供多个离散电荷分组。 选择电荷分组的极性，以便在第二电容器两端的电压方向上增加或减小第一电容器两端的电压。 当两个电容器两端的电压相等时，差分比较器产生指示转换操作结束的输出信号。 选择第一和第二电容器的参数，使得由于衬底中的热感应漏电流而增加或从第二电容器中减去的电荷量基本上等于添加到或从第一电容器中减去的电荷量 作为热感应漏电流的结果。

公开(公告)号：US3953745A

公开(公告)日：1976-04-27

申请号：US534262

申请日：1974-12-19

Applicant: Walter H. Bailey

Inventor： Walter H. Bailey

IPC: G11C19/18 ,  G11C19/28 ,  G11C27/04 ,  H01L27/105 ,  H01L29/423 ,  H01L29/768 ,  H03H11/26 ,  H03H15/02 ,  H03K17/687 ,  H03K25/00

CPC classification number: H01L29/42396 ,  G11C19/186 ,  G11C19/285 ,  G11C19/287 ,  G11C27/04 ,  H01L27/1057 ,  H01L29/768 ,  H01L29/76816 ,  H03H15/02 ,  H03H2015/026

Abstract: An improved charge transfer device signal processing system is disclosed. In one aspect of the invention the signal at each node of a bucket brigade delay line is detected to provide a continuous output signal over a major portion of a cycle of a multiphase clock. In a different aspect of the invention the signals detected at the respective nodes of a matched filter are selectively summed to negative or positive summation busses to provide an electronically programmable matched filter. In still a different aspect of the invention a charge transfer device matched filter is provided in which both the magnitude and sign of the respective weighted signals can be selectively controlled. There is also provided an improved configuration for detecting the charge required to recharge the two different electrode portions of a split electrode weighted charge coupled device matched filter.

公开(公告)号：US3621279A

公开(公告)日：1971-11-16

申请号：US3621279D

申请日：1970-01-28

Applicant: IBM

Inventor： JEN TEH-SEN ,  PRICER WILBUR D ,  VOGL NORBERT G JR

IPC: G11C19/18 ,  H01L27/088 ,  G11C19/00

CPC classification number: G11C19/186 ,  H01L27/088

Abstract: A dynamic shift register is disclosed for providing large capacity storage of digital data information in a small-volume solid-state package. A unique high-density approach is taken, involving a cell comprising n subcells capable of storing n-1 bits of data. The cells are fabricated preferably of field effect transistors embedded in a semiconductor wafer or monolith.

公开(公告)号：US20170345517A1

公开(公告)日：2017-11-30

申请号：US15538007

申请日：2016-02-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Junwei WANG ,  Bin FENG

IPC: G11C19/28 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0248 ,  G11C19/186 ,  G11C19/188

Abstract: A precharging circuit, a scanning driving circuit, an array substrate, and a display device are provided. The precharging circuit includes an input end, an output end, and further includes a switching unit, first pull-up unit, and second pull-up unit. The switching unit has first end connected to first node; second end connected to the input end, and third end connected to second node, and is used for conducting the second end and the third end when first end is at high level; first pull-up unit has first end connected to the output end and second end connected to first node, and is used for pulling up potential of second end when first end is at high level; second pull-up unit has first end connected to second node and second end connected to output end, is used for pulling up potential of second end when first end is at high level.

公开(公告)号：US20170330633A1

公开(公告)日：2017-11-16

申请号：US15526213

申请日：2016-10-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tuo SUN ,  Zhanjie MA

IPC: G11C19/18 ,  G11C19/28 ,  G09G1/02

CPC classification number: G11C19/186 ,  G09G1/02 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: The present disclosure provides a shift register, including: an input circuit, electrically connected to a triggering signal line that provides a triggering signal, a first clock signal line that provides a first clock signal, and a first node; configured for controlling whether the triggering signal is outputted to the first node based on the first clock signal; a control circuit, electrically connected to the first node, a second node, the first clock signal line, a second clock signal line that provides a second clock signal, and a turn-on signal line that provides a turn-on signal, configured for controlling whether the turn-on signal is outputted to the second node; and an output circuit, electrically connected to the first node, the second node, a first signal line that provides a first signal, a second signal line that provides a second signal, and a driving signal output line that outputs a driving signal.

公开(公告)号：US20170098413A1

公开(公告)日：2017-04-06

申请号：US15283588

申请日：2016-10-03

Applicant: LG Display Co., Ltd.

Inventor： Youngjang LEE ,  Jeanhan YOON

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/3275 ,  H01L27/32 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/3275 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2330/021 ,  G11C19/186 ,  G11C19/28

Abstract: Provided are an organic light-emitting diode (OLED) display and method of driving the same. An OLED display includes: a display panel including a plurality of pixels, each pixel including an OLED, an emission timing of each pixel being controlled in response to an EM signal, a shift register configured to generate an anti-phase EM signal based on gate shift clocks, and an inverter configured to: invert a phase of the anti-phase EM signal based on emission shift clocks, and generate the EM signal, wherein a driving frequency of the shift register and a driving frequency of the inverter are lower in a low-speed driving mode than in a normal driving mode, and wherein in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.

公开(公告)号：US20140344544A1

公开(公告)日：2014-11-20

申请号：US14450705

申请日：2014-08-04

Applicant: Tado Nakamura ,  Michael J. Flynn

Inventor： Tadao Nakamura ,  Michael J. Flynn

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C19/184 ,  G11C19/186 ,  G11C19/188 ,  G11C19/28 ,  G11C19/287

Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

Abstract translation: 公开了一种具有存储器单元阵列的行进存储器。 每个存储器单元具有位级单元的序列。 每个位电平单元具有转移晶体管，其具有通过第一延迟元件连接到时钟信号供给线的第一主电极和连接到位于第一延迟元件的第一相邻位电平的输出端的控制电极 通过第二延迟元件的存储器单元的阵列的输入侧。 每个位电平单元还具有复位晶体管，其具有连接到转移晶体管的第二主电极的第一主电极，连接到时钟信号供给线的控制电极和连接到 地面潜力。 每个位电平单元还具有与复位晶体管并联连接的电容器。