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8 条记录 (耗时 0.014 秒)

    Non-overlapping two-phase clock generator utilizing floating inverters
    2.
    发明授权
    Non-overlapping two-phase clock generator utilizing floating inverters 失效
    不重叠的两相时钟发生器利用浮动逆变器

    公开(公告)号：US5047659A

    公开(公告)日：1991-09-10

    申请号：US576814

    申请日：1990-09-04

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： H03K5/151

    CPC分类号： H03K5/1515

    摘要： A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.

    摘要翻译： 两相时钟发生器通过利用第一和第二信号路径中的门延迟从单极输入时钟产生非重叠的两相时钟。 每个信号路径的输出通过交叉耦合的反馈路径馈送回相应的另一信号路径中的逻辑门。 每个逻辑门是具有连接到电源电压的第一电源端的浮动逆变器，并且具有作为来自另一个信号路径的输出的相应反馈信号的馈电点的第二电源端。

    Circuit arrangement for calculating product sums
    3.
    发明授权
    Circuit arrangement for calculating product sums 失效
    用于计算产品系列的电路布置

    公开(公告)号：US5111422A

    公开(公告)日：1992-05-05

    申请号：US577394

    申请日：1990-09-04

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： G06F7/53 ,  G06F7/527 ,  G06F7/544

    CPC分类号： G06F7/5443

    摘要： By using a basic cell (g), an overall array (ga) for forming n products from pairs of multidigit binary numbers Amn, Bkn and for adding these n products is formed, with the formation and summation of all partial products being interleaved row by row. Each basic cell contains a delay unit for the A-coefficient inputs controlled by a half clock signal, an undelayed through connection for the B-coefficient input, an added fed via respective delay units with a sum input, a carry input, and a summation input, and a logic gate which combines the B-coefficient with the undelayed A-coefficients to form the partial product thereof and provides the partial product to the summation input of the adder.

    摘要翻译： 通过使用基本单元格（g），形成用于从多对二进制数Amn，Bkn对形成n个乘积的总体阵列（ga），并且用于添加这些n个乘积，并且所有部分乘积的形成和求和被交替排列 行。 每个基本单元包含用于由半时钟信号控制的A系数输入的延迟单元，用于B系数输入的不延迟的连接，通过具有和输入的相应延迟单元，进位输入和加法 输入和逻辑门，其将B系数与未延迟的A系数组合以形成其部分乘积，并将加法器的求和输入提供部分乘积。

    Two-dimensional analog memory
    4.
    发明授权
    Two-dimensional analog memory 失效
    二维模拟记忆

    公开(公告)号：US4272831A

    公开(公告)日：1981-06-09

    申请号：US93959

    申请日：1979-11-14

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： G11C19/28 ,  G11C27/04 ,  H04N5/45 ,  H04N5/907 ,  G11C11/40

    CPC分类号： H04N5/45 ,  G11C19/287 ,  G11C27/04 ,  H04N5/907

    摘要： Two-dimensional analog memory monolithically integrated with insulated-gate field-effect transistors, operating on the charge-transfer, and more particularly on the bucket-brigade principle, for temporarily storing the signals originating with the two half pictures of a (TV) video signal.

    摘要翻译： 与电荷传输操作的绝缘栅场效应晶体管单片集成的二维模拟存储器，更具体地，涉及桶式存储器原理，用于临时存储源自（TV）视频的两个半图像的信号 信号。

    CMOS inverter chain
    5.
    发明授权
    CMOS inverter chain 失效
    CMOS逆变链

    公开(公告)号：US4734597A

    公开(公告)日：1988-03-29

    申请号：US938632

    申请日：1986-12-05

    申请人： Manfred F. Ullrich ,  Arnold Uhlenhoff

    发明人： Manfred F. Ullrich ,  Arnold Uhlenhoff

    IPC分类号： H03K5/26 ,  H03L1/00 ,  H03K19/20 ,  H03K19/017 ,  H03K19/096

    CPC分类号： H03K5/26 ,  H03L1/00

    摘要： A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.

    摘要翻译： CMOS逆变器链包括N-和P-逆变器的交替串联连接。 N反相器是在P型晶体管和N型晶体管之间采用N型中间晶体管的常规类型的CMOS反相器; 然而，P逆变器是在P型晶体管和N型晶体管之间采用P-中间晶体管的CMOS反相器。 中间晶体管的栅极由时钟信号互连和控制，而逆变器输入由每个逆变器的P-晶体管和N晶体管的互连栅极构成。 这样的逆变器链可以例如用作数字脉冲宽度鉴别器作为最终位置计数器，用作用于补偿输入脉冲中的信号丢失的电路，或者用于实现环形振荡器同步。

    Digital integrated circuit for the color matrix of a color-television set
    6.
    发明授权
    Digital integrated circuit for the color matrix of a color-television set 失效
    用于彩色电视机的彩色矩阵的数字集成电路

    公开(公告)号：US4568968A

    公开(公告)日：1986-02-04

    申请号：US750976

    申请日：1985-07-01

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： G21C15/243 ,  H04N9/67 ,  H04N9/76

    CPC分类号： H04N9/67

    摘要： The circuit contains three multipliers/adders for the luminance signal (y) and the two color-difference signals (r-y, b-y). For the output signals of these stages, four parallel adders are provided. The multipliers for the factors -0.51 and -0.19, which would be required in accordance with the color-television-system formula y=0.3r+0.59g+0.11b are rendered unnecessary because, among other things, the input signals are provided with correction factors (k, L, m) and correction addends (d, e, f) in the multipliers/adders in view of a presettable color overload.

    摘要翻译： 该电路包含用于亮度信号（y）和两个色差信号（r-y，b-y）的三个乘法器/加法器。 对于这些级的输出信号，提供四个并行加法器。 根据彩色电视系统公式y = 0.3r + 0.59g + 0.11b需要的因子-0.51和-0.19的乘数是不必要的，因为除了别的以外，输入信号被提供 鉴于可预设的颜色过载，乘法器/加法器中的校正因子（k，L，m）和校正加数（d，e，f）。

    Output circuit for bucket-brigade devices
    7.
    发明授权
    Output circuit for bucket-brigade devices 失效
    铲斗装置的输出电路

    公开(公告)号：US4254345A

    公开(公告)日：1981-03-03

    申请号：US040828

    申请日：1979-05-21

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： G11C19/18 ,  H01L27/105 ,  G11C19/28 ,  H01L29/78

    CPC分类号： G11C19/186 ,  H01L27/1055

    摘要： To reduce the D.C drift of bucket-brigade devices having common output circuits (emitter follower), an output circuit is provided having an additional transistor and an additional capacitor. The terminal on the gate side of the capacitor associated with the last delaying transistor is not connected to the gate terminal but to the source terminal of the output transistor, the gate terminal of the terminating transistor is applied via the additional capacitor to that particular clock signal to which the penultimate delaying transistor is applied, and the drain terminal of the terminating transistor, via an enhancement-type transistor of the same conductivity, connected as a diode by directly connecting both the drain and the gate terminals, is connected to the gate terminal thereof.

    摘要翻译： 为了减少具有公共输出电路（射极跟随器）的斗式装置的D.C漂移，提供具有附加晶体管和附加电容器的输出电路。 与最后延迟晶体管相关的电容器的栅极侧的端子不连接到栅极端子，而是连接到输出晶体管的源极端子，端接晶体管的栅极端子经由附加电容器施加到该特定的时钟信号 通过直接连接两个漏极和栅极端子连接作为二极管的相同导电性的增强型晶体管，终端晶体管的漏极端子连接到栅极端子 其中。