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    CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME
    3.
    发明申请
    CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
    具有被动装置的芯片结构及其形成方法

    公开(公告)号：US20130214387A1

    公开(公告)日：2013-08-22

    申请号：US13851050

    申请日：2013-03-26

    申请人： Megica Corporation

    发明人： Mou-Shiung Lin

    IPC分类号： H01L27/04 ,  H01L21/82

    CPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/82 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/19104 ,  H01L2924/00

    摘要： The present disclosure provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.

    摘要翻译： 本公开提供了一种用电阻器形成芯片结构的方法。 提供半导体衬底并具有表面。 在半导体衬底的表面上形成多个电子器件和电阻器。 在半导体衬底上形成多个电介质层和多个电路层。 电介质层堆叠在半导体衬底上并具有多个通孔。 电路层中的每一个分别设置在相应的一个电介质层上，其中电路层通过通孔彼此电连接并与电子器件电连接。 在电介质层和电路层上形成钝化层。 在钝化层上形成电路线，其中电路线通过钝化层并与电阻器电连接。

    Multiple selectable function integrated circuit module
    7.
    发明授权
    Multiple selectable function integrated circuit module 有权
    多功能集成电路模块

    公开(公告)号：US08471389B2

    公开(公告)日：2013-06-25

    申请号：US13197633

    申请日：2011-08-03

    申请人： Mou-Shiung Lin

    发明人： Mou-Shiung Lin

    IPC分类号： H01L23/48

    CPC分类号： H01L22/20 ,  H01L22/22 ,  H01L23/5382 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L2924/014

    摘要： An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions arc selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module. The second level module substrate has connector pins to provide physical and electrical connections between the external circuitry and the wiring connections on the second level substrate.

    摘要翻译： 集成电路模块具有已知的具有可选择功能的良好集成电路管芯的通用功能。 可选功能在已知的良好集成电路管芯封装期间被选择。 已知的良好的集成电路管芯安装到第二级衬底。 第二级衬底具有连接到已知的良好集成电路管芯的输入/输出焊盘的接线连接器，其选择所需的输入功能和输出功能。 此外，第二级基板上的布线连接提供信号路径，以将信号传送到期望的输入功能，并从期望的输出功能传送信号，并向常用功能发送信号。 此外，接线连接形成输入/输出焊盘和外部电路之间的连接。 为了选择所需的输入功能和所需的输出功能，适当的逻辑状态被应用于连接到功能选择器的输入/输出焊盘以配置集成电路模块的功能操作。 第二级模块衬底具有连接器引脚，以在外部电路和第二级衬底上的接线连接之间提供物理和电连接。

    Method for making high-performance RF integrated circuits
    8.
    发明授权
    Method for making high-performance RF integrated circuits 有权
    制造高性能RF集成电路的方法

    公开(公告)号：US08384508B2

    公开(公告)日：2013-02-26

    申请号：US13077009

    申请日：2011-03-31

    申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

    发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

    IPC分类号： H01F5/00 ,  H01F27/28

    CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/5227 ,  H01L28/10 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.

    摘要翻译： 提供了一种新的制造半导体电感器的方法和结构。 在本发明的第一实施例中，半导体衬底在无源表面区域中设有划线，并且在被动区域周围设有有源电路。 在基板的被动表面上至少形成一个接合垫，该接合垫靠近划线的每侧。 沉积一层绝缘层，在该绝缘层上沉积一层电介质，至少一个接合焊盘设置在刻划线两边的电介质层的表面上。 在电介质层的表面上的划线的每侧形成至少一个电感器。 一层钝化层沉积在电介质层上。 通过将钝化层的表面与玻璃面板接合来将衬底附接到玻璃面板。 衬底从衬底的背面锯切，与划刻线对准。 通过蚀刻去除在划线下面的衬底的被动表面中残留的位置的硅，沿着划线分离玻璃面板。 在本发明的第二个实施例中，电感器被形成在沉积在钝化层上的聚合物厚层的表面上。