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1.发明授权Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug 失效带有非绝缘缺口栅极盖层的引出源极漏极漏极，漏极侧壁钝化并填充有电介质插塞公开(公告)号：US07700425B2
公开(公告)日：2010-04-20
申请号：US11585361
申请日：2006-10-23
IPC分类号： H01L21/8238
CPC分类号： H01L29/66772 , H01L29/78618
摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
摘要翻译： 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 通过将掺杂剂注入到其表面中，在栅电极的顶表面中形成薄的非晶硅覆盖层。 凹口蚀刻到盖层的周边。 在凹口中形成介电材料塞。 栅电极的侧壁被覆盖一部分插塞的侧壁间隔物覆盖，以消除栅极多晶硅的暴露，从而避免在形成升高的源极/漏极区域期间形成假外延生长。
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2.发明授权Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness 失效在硅的薄膜的表面上的凹部上形成电子器件的方法被蚀刻到精确的厚度公开(公告)号：US06930030B2
公开(公告)日：2005-08-16
申请号：US10453080
申请日：2003-06-03
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3065 , H01L21/3213 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L21/302
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/2658 , H01L21/28114 , H01L21/3065 , H01L21/32137 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/7834
摘要： A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.
摘要翻译： 用于精确稀化以在晶体硅层中形成精确深度的凹槽的方法，其可用于形成诸如MOSFET器件的各种器件，包括以下步骤。 在硅层的顶表面上形成具有窗口的图案掩模。 在窗口下方的硅层的顶表面形成非晶化区域。 选择性地蚀刻去除硅层的非晶化区域，以在硅层表面形成凹陷，并去除图形掩模。 在MOSFET器件的情况下，在图案掩模下形成硬掩模，窗口延伸穿过其中。 然后通过硬掩模在窗口中产生侧壁间隔物，并在窗口中形成栅极电极堆叠。 然后去除硬掩模，形成源极/漏极延伸部分，光晕和区域加上硅化物，并完成MOSFET器件。
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3.发明授权STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能公开(公告)号：US07479688B2
公开(公告)日：2009-01-20
申请号：US10751831
申请日：2004-01-05
IPC分类号： H01L29/72
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在又一实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。
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4.发明授权STI stress modification by nitrogen plasma treatment for improving performance in small width devices 失效通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能公开(公告)号：US06887798B2
公开(公告)日：2005-05-03
申请号：US10250047
申请日：2003-05-30
IPC分类号： H01L21/318 , H01L21/762 , H01L29/10 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。
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公开(公告)号：US20100330763A1
公开(公告)日：2010-12-30
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。
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6.发明申请公开(公告)号：US20080233687A1
公开(公告)日：2008-09-25
申请号：US12132698
申请日：2008-06-04
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。
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7.发明授权In situ doped embedded sige extension and source/drain for enhanced PFET performance 有权用于增强PFET性能的原位掺杂嵌入式扩展和源极/漏极公开(公告)号：US07176481B2
公开(公告)日：2007-02-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。
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8.发明授权公开(公告)号：US06815282B2
公开(公告)日：2004-11-09
申请号：US10460717
申请日：2003-06-12
IPC分类号： H01L2972
CPC分类号： G11C11/412 , H01L27/1104 , H01L27/1203
摘要： Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
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公开(公告)号：US08017483B2
公开(公告)日：2011-09-13
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。
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10.发明申请DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD 审中-公开具有线性和相关方法之间的主要平面界面的双应力衬里结构公开(公告)号：US20090090974A1
公开(公告)日：2009-04-09
申请号：US11868567
申请日：2007-10-08
IPC分类号： H01L27/092 , H01L21/311
CPC分类号： H01L21/823807 , H01L21/31111 , H01L29/7843
摘要： A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween.
摘要翻译： 公开了一种在衬垫之间具有基本平坦的界面的双重应力衬垫结构和相关方法。 在一个实施例中，双应力衬垫结构可以包括在NFET上的拉伸应力衬垫，NFET包括与其相邻的PFET; 以及PFET上的压应力衬垫，其中所述压应力衬垫的上表面在其间的界面处与所述拉伸应力衬垫的上表面基本上是平面的。
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