发明授权
US07700425B2 Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug
失效
带有非绝缘缺口栅极盖层的引出源极漏极漏极,漏极侧壁钝化并填充有电介质插塞
- 专利标题: Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug
- 专利标题(中): 带有非绝缘缺口栅极盖层的引出源极漏极漏极,漏极侧壁钝化并填充有电介质插塞
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申请号: US11585361申请日: 2006-10-23
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公开(公告)号: US07700425B2公开(公告)日: 2010-04-20
- 发明人: Tina J. Wagner , Werner A. Rausch , Sadanand V. Deshpande
- 申请人: Tina J. Wagner , Werner A. Rausch , Sadanand V. Deshpande
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Graham S. Jones, II; H. Daniel Schnurmann
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
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